HD6477021X20V Renesas Electronics America, HD6477021X20V Datasheet - Page 170

• Manufacturer Part Number: HD6477021X20V
• Description: MCU 5V 32K PB-FREE 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7020r

Specifications of HD6477021X20V

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: OTP
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

enter the self-refresh mode when the CAS and RAS signals are output as shown in figure 8.31. See
section 20.3.3, Bus Timing, for details. The DRAM self-refresh mode is cleared when the
RMODE bit in the RCR is cleared to 0 (figure 8.31). The RFSHE bit should be left at 1 when this
is done. Some DRAM vendors recommend that after exiting the self-refresh mode, all row
addresses should be refreshed again. This can be done using the BCR’s CBR refresh function to
set all row addresses for refresh in software.
To access a DRAM area in the self-refresh mode, clear the RMODE bit to 0 and exit the self-
refresh mode.
The LSI can be kept in the self-refresh state and shifted to standby mode by setting it to self-
refresh mode, setting the standby bit (SBY) of the standby control register (SBYCR) to 1, and then
executing a SLEEP instruction.
Refresh Requests and Bus Cycle Requests: When a CAS-before-RAS refresh or self-refresh is
requested during bus cycle execution, parallel execution is sometimes possible. Table 8.10
describes operation when the refresh and bus cycle are in contention.
150 RENESAS
RAS
CAS
CK
T
Rp
Figure 8.31 Output Timing of Self-Refresh Signal
T
Rr
T
Rc
T
Rcc