HD6477021X20V Renesas Electronics America, HD6477021X20V Datasheet - Page 215

• Manufacturer Part Number: HD6477021X20V
• Description: MCU 5V 32K PB-FREE 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7020r

Specifications of HD6477021X20V

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: OTP
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

• Burst Mode
Relationship between Request Modes and Bus Modes by DMA Transfer Category: Table 9.6
shows the relationship between request modes and bus modes by DMA transfer category.
196 RENESAS
Figure 9.10 Transfer Example in the Cycle-Steal Mode (Dual address mode, DREQ level
Bus cycle
Once the bus right is obtained, the transfer is performed continuously until the transfer end
condition is satisfied. In the external request mode with low level detection of the DREQ pin,
however, when the DREQ pin is driven high, the bus passes to the other bus master after the
bus cycle of the DMAC that currently has an acknowledged request ends, even if the transfer
end conditions have not been satisfied.
The burst mode cannot be used when the serial communications interface (SCI) is the transfer
request source. Figure 9.11 shows an example of DMA transfer timing in the burst mode. The
transfer conditions shown in the figure are:
Figure 9.11 Transfer Example in the Burst Mode (Single address mode, DREQ level
Bus cycle
DREQ
Single address mode
DREQ level detection
DREQ
CPU
CPU
CPU
CPU
CPU
CPU
DMAC DMAC DMAC DMAC DMAC
DMAC DMAC
Read
detection)
detection)
Bus right returned to CPU
Write
CPU
DMAC DMAC
Read
Write
DMAC
CPU
CPU