HD6477021X20V Renesas Electronics America, HD6477021X20V Datasheet - Page 66
HD6477021X20V
Manufacturer Part Number
HD6477021X20V
Description
MCU 5V 32K PB-FREE 100-TQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7020r
Datasheet
1.HD6417020SVX12IV.pdf
(511 pages)
Specifications of HD6477021X20V
Core Processor
SH-1
Core Size
32-Bit
Speed
20MHz
Connectivity
EBI/EMI, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
32KB (32K x 8)
Program Memory Type
OTP
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD6477021X20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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On a power-on reset, all CPU internal states and on-chip peripheral module registers are
initialized. In a manual reset, all CPU internal states and on-chip peripheral module registers, with
the exception of the bus state controller (BSC) and pin function controller (PFC), are initialized.
On a manual reset, the BSC is not initialized, so the refresh operation will continue.
Exception Processing State: Exception processing is a transient state that occurs when the CPU’s
processing state flow is altered by exception processing sources such as resets or interrupts.
For a reset, the initial values of the program counter PC (execution start address) and stack pointer
SP are fetched from the exception processing vector table and stored; the CPU then branches to
the execution start address and execution of the program begins.
For an interrupt, the stack pointer (SP) is accessed and the program counter (PC) and status
register (SR) are saved to the stack area. The exception service routine start address is fetched
from the exception processing vector table; the CPU then branches to that address and the program
starts executing, thereby entering the program execution state.
Program Execution State: In the program execution state, the CPU sequentially executes the
program.
Power-Down State: In the power-down state, the CPU operation halts and power consumption
declines. The SLEEP instruction places the CPU in the power-down state. This state has two
modes: sleep mode and standby mode. This is described in more detail in section 2.5.1, Power-
Down State.
Bus Release State: In the bus release state, the CPU releases rights to the bus to the device that
has requested them.
2.5.2
Power-Down State
In addition to the ordinary program execution states, the CPU also has a power-down state in
which CPU operation halts and power consumption is lowered. There are two power-down state
modes: sleep mode and standby mode.
Sleep Mode: When the standby bit SBY (in the standby control register SBYCR) is cleared to 0
and a SLEEP instruction executed, the CPU moves from program execution state to sleep mode.
In the sleep mode, the CPU halts and the contents of its internal registers and the data in on-chip
RAM are stored. The on-chip peripheral modules other than the CPU do not halt in the sleep
mode.
To return from sleep mode, use a reset, any interrupt, or a DMA address error; the CPU returns to
ordinary program execution state through the exception processing state.
RENESAS43
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