M30290FAHP#U5A Renesas Electronics America, M30290FAHP#U5A Datasheet - Page 303

• Manufacturer Part Number: M30290FAHP#U5A
• Description: IC M16C/29 MCU FLASH 96K 80LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/Tiny/29r

Specifications of M30290FAHP#U5A

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 71
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 27x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 80-LQFP
• For Use With: R0K330290S000BE - KIT EVAL STARTER FOR M16C/29M30290T2-CPE - EMULATOR COMPACT M16C/26A/28/29M30290T2-CPE-HP - EMULATOR COMPACT FOR M16C/TINY
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R
R
M
16.8 I
e
E
1
. v
J
6
0
The S2D0 register controls the START/STOP condition detections.
16.8.1 Bit0-Bit4: START/STOP Condition Setting Bits (SSC0-SSC4)
16.8.2 Bit5: SCL/SDA Interrupt Pin Polarity Select Bit (SIP)
16.8.3 Bit6 : SCL/SDA Interrupt Pin Select Bit (SIS)
16.8.4 Bit7: START/STOP Condition Generation Select Bit (STSPSEL)
1
9
C
1 .
B
The SCL release time and the set-up and hold times are mesured on the base of the I
(V
I
the SCL release time, the set-up and hold times by the system clock frequency (See Table 16.10). Do
not set odd numbers or 00000
SSC4 to SSC0 at each oscillation frequency in standard clock mode. The detection of START/STOP
conditions starts immediately after the ES0 bit in the S1D0 register is set to 1 (I
The The SIP bit detect the rising edge or the falling edge of the SCL
interrupts. The SIP bit selects the polarity of the SCL
The SIS bit selects a pin to enable SCL/SDA interrupt.
NOTE:
The STSPSEL bit selects the set-up/hold times, based on the I2C system clock cycles, when the START/
STOP condition is generated (See Table 16.8). Set the STSPSEL bit to 1 if the I
frequency is over 4MHz.
2 /
2
0
2
C bus system clock select bits. It is necessary to set bits SSC4 to SSC0 to the appropriate value to set
9
1
IIC
M
0
2
1. The SCL/SDA interrupt request may be set when changing the SIP, SIS and ES0 bit settings in the
G
1
). Therefore, the detection conditions changes, depending on the oscillation frequency (X
r a
C0 START/STOP Condition Control Register (S2D0 Register)
0 -
o r
S1D0 register. When using the SCL/SDA interrupt, set the above bits, while the SCL/SDA interrupt
is disabled. Then, enable the SCL/SDA interrupt after setting the SCL/SDA bit in the IR register to 0.
3 .
1
u
, 0
1
p
2
2
0
0
7
page 277
f o
4
2
5
8
to bits SSC4 to SSC0. Table 16.2 shows the reference value to bits
MM
or the SDA
MM
MM
or SDA
for interrupt.
2
MM
C bus interface enabled).
to generate SCL/SDA
2
2
C bus system clock
C bus system clock
IN
) and the