M30290FAHP#U5A Renesas Electronics America, M30290FAHP#U5A Datasheet - Page 220

• Manufacturer Part Number: M30290FAHP#U5A
• Description: IC M16C/29 MCU FLASH 96K 80LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/Tiny/29r

Specifications of M30290FAHP#U5A

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 71
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 27x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 80-LQFP
• For Use With: R0K330290S000BE - KIT EVAL STARTER FOR M16C/29M30290T2-CPE - EMULATOR COMPACT M16C/26A/28/29M30290T2-CPE-HP - EMULATOR COMPACT FOR M16C/TINY
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R
R
M
e
E
1
. v
J
Figure 14.19 Serial Data Logic Switching
Figure 14.20 T
6
0
C
1
9
1 .
B
2 /
0
14.1.2.4 Serial Data Logic Switching Function (UART2)
14.1.2.5 TxD and RxD I/O Polarity Inverse Function (UART2)
2
9
1
(1) When the U2LCH bit in the U2C1 register is set to 0 (no reverse)
(2) When the U2LCH bit in the U2C1 register is set 1 (reverse)
M
The data written to the U2TB register has its logic reversed before being transmitted. Similarly, the
received data has its logic reversed when read from the U2RB register. Figure 14.19 shows serial
data logic.
This function inverses the polarities of the T
input/output data (including the start, stop and parity bits) are inversed. Figure 14.20 shows the T
pin output and R
0
Transfer clock
G
NOTE:
Transfer clock
1
r a
0 -
o r
3 .
(no reverse)
1. This applies to the case where the CKPOL bit in the U2C0 register is set to 0
1
u
(1) When the IOPOL bit in the U2MR register is set to 0 (no reverse)
, 0
(2) When the IOPOL bit in the U2MR register is set to 1 (reverse)
1
(reverse)
p
(transmit data output at the falling edge of the transfer clock), the UFORM bit in
the U2C0 register is set to 0 (LSB first), the STPS bit in the U2MR register is set
to 0 (1 stop bit) and the PRYE bit in the U2MR register is set to 1 (parity
NOTE:
2
Transfer clock
Transfer clock
2
TxD
TxD
0
1. This applies to the case where the UFORM bit in the U2C0 register is set
(no reverse)
(no reverse)
X
0
D and R
7
2
(reverse)
to 0 (LSB first), the STPS bit in the U2MR register is set to 0 (1 stop bit)
and the PRYE bit in the U2MR register is set to 1 (parity enabled).
2
(reverse)
RxD
RxD
TxD
TxD
“H”
“H”
“H”
“L”
page 194
“H”
“L”
“L”
“L”
X
2
2
2
2
D pin input polarity inverse.
“H”
“L”
“H”
“L”
“H”
“L”
“H”
“L”
“H”
“H”
“L”
“L”
X
D I/O Polarity Inverse
f o
ST
ST
4
ST
ST
ST
ST
5
8
D0
D0
D0
D0
D0
D0
D1
D1
D1
D1
D1
D1
D2
D2
D2
D2
D2
D2
X
D2 pin output and R
D3
D3
D3
D3
D3
D3
D4
D4
D4
D4
D4
D4
D5
D5
D5
D5
D5
D5
D6
D6
D6
D6
D6
D6
X
D2 pin input. The logic levels of all
D7
D7
D7
D7
D7
D7
P
P
P
P
P
P
SP
SP
SP
SP
SP
SP
ST: Start bit
P: Parity bit
SP: Stop bit
ST: Start bit
P: Parity bit
SP: Stop bit
X
D