M30290FAHP#U5A Renesas Electronics America, M30290FAHP#U5A Datasheet - Page 114

• Manufacturer Part Number: M30290FAHP#U5A
• Description: IC M16C/29 MCU FLASH 96K 80LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/Tiny/29r

Specifications of M30290FAHP#U5A

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 71
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 27x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 80-LQFP
• For Use With: R0K330290S000BE - KIT EVAL STARTER FOR M16C/29M30290T2-CPE - EMULATOR COMPACT M16C/26A/28/29M30290T2-CPE-HP - EMULATOR COMPACT FOR M16C/TINY
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

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Table 9.6 PC Value Saved in Stack Area When Address Match Interrupt Request Is Acknowledged
Table 9.7 Relationship Between Address Match Interrupt Sources and Associated Registers
Figure 9.14 AIER Register, RMAD0 and RMAD1 Registers
Value of the PC that is saved to the stack area : Refer to “Saving Registers”.
Op-code is an abbreviation of Operation Code. It is a portion of instruction code.
Refer to Chapter 4 Instruction Code/Number of Cycles in M16C/60, M16C/20 Series Software Manual. Op-code is shown
as a bold-framed figure directly below the Syntax.
6
0
Address match interrupt 0
Address match interrupt 1
• 2-byte op-code instruction
• 1-byte op-code instructions which are followed:
Instructions other than the above
C
1
9
Address match interrupt sources Address match interrupt enable bit
1 .
B
2 /
ADD.B:S
OR.B:S
STNZ.B
CMP.B:S
JMPS
MOV.B:S
0
2
(b23)
Address Match Interrupt Register i (i = 0 to 1)
b7
9
b7
1
Address Match Interrupt Enable Register
M
0
G
1
r a
b6
0 -
o r
3 .
1
u
b5
, 0
1
p
2
(b19)
2
b4
b3
0
#IMM8,dest
#IMM8,dest
#IMM8,dest
#IMM8,dest
#IMM8
#IMM,dest (However, dest=A0 or A1)
0
Instruction at the address indicated by the RMADi register
b3
7
b2
(b16)
b0 b7
b1
(b15)
page 88
b0
SUB.B:S
MOV.B:S
STZX.B
PUSHM
JSRS
f o
4
Address setting register for address match interrupt
Nothing is assigned. If necessary, set to 0.
When read, the content is undefined
Bit Symbol
5
8
(b7-b2)
AIER0
AIER1
AIER0
AIER1
Symbol
AIER
(b8)
b0
#IMM8,dest
#IMM8,dest
#IMM81,#IMM82,dest
src
#IMM8
b7
Address match interrupt 0
enable bit
Address match interrupt 1
enable bit
Nothing is assigned. If necessary, set to 0.
When read, the content is undefined
Function
Address
0009
Bit Name
16
b0
AND.B:S
STZ.B
POPM dest
Symbol
RMAD0
RMAD1
After Reset
XXXXXX00
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
#IMM8,dest
#IMM8,dest
RMAD0
RMAD1
Address match interrupt register
Address
0012
0016
2
Function
00000
16
16
to 0014
to 0010
Setting Range
16
Value of the PC that is
saved to the stack area
The address
indicated by the
RMADi register +2
The address
indicated by the
RMADi register +1
to FFFFF
16
16
After Reset
X00000
X00000
16
RW
RW
RW
RW
RW
16
16