M30290FAHP#U5A Renesas Electronics America, M30290FAHP#U5A Datasheet - Page 204

• Manufacturer Part Number: M30290FAHP#U5A
• Description: IC M16C/29 MCU FLASH 96K 80LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/Tiny/29r

Specifications of M30290FAHP#U5A

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 71
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 27x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 80-LQFP
• For Use With: R0K330290S000BE - KIT EVAL STARTER FOR M16C/29M30290T2-CPE - EMULATOR COMPACT M16C/26A/28/29M30290T2-CPE-HP - EMULATOR COMPACT FOR M16C/TINY
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R
R
M
e
E
1
. v
J
Figure 14.8 U2SMR and U2SMR2 Registers
6
0
C
1
9
1 .
B
2 /
0
2
9
1
NOTES:
UART2 Special Mode Register
M
0
b7 b6 b5 b4 b3 b2 b1 b0
UART2 Special Mode Register 2
G
b7 b6 b5 b4 b3 b2 b1 b0
1
r a
1: The BBS bit is set to 0 by writing 0 by program. (Writing 1 has no effect).
2: When a transfer begins, the SSS bit is set to 0 (Not synchronized to RxD
0 -
o r
3 .
1
u
, 0
1
p
2
2
0
0
0
7
page 178
ABSCS
Symbol
ACSE
SSS
ABC
BBS
(b3)
(b7)
IICM
IICM2
CSC
SWC
ALS
STAC
SWC2
SDHI
Symbol
Bit
(b7)
Bit
f o
Symbol
U2SMR2
Arbitration lost detecting
flag control bit
Bus busy flag
Reserved bit
Bus collision detect
sampling clock select bit
Auto clear function
select bit of transmit
enable bit
Transmit start condition
select bit
4
I
2
Nothing is assigned. If necessary, set to 0. When read, the content is undefined
Symbol
U2SMR
5
C bus mode select bit
I C bus mode select bit 2
Clock-synchronous bit
SCL
SDA
UART initialization bit
SCL
SDA
Nothing is assigned. If necessary, set to 0.
When read, the content is undefined
2
8
2
2
2
2
Bit Name
wait output bit
wait output bit 2
output stop bit
output disable bit
Bit Name
Address
0376
Address
0377
16
0 : Rising edge of transfer clock
1 : Underflow signal of timer A0
0 : Other than I
1 : I
0 : No auto clear function
1 : Auto clear at occurrence of bus collision
0 : Update per bit
1 : Update per byte
0 : STOP condition detected
1 : START condition detected (busy)
Set to 0
0 : Not synchronized to RxD
1 : Synchronized to RxD
16
2
Refer to Table 14.13
0 : Disabled
1 : Enabled
0 : Disabled
1 : Enabled
0 : Disabled
1 : Enabled
0 : Disabled
1 : Enabled
0: Transfer clock
1: “L” output
0: Enabled
1: Disabled (high impedance)
C bus mode
After Reset
X0000000
2
).
2
C bus mode
After Reset
X0000000
2
2 (2)
2
Function
Function
2
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
(1)