M30290FAHP#U5A Renesas Electronics America, M30290FAHP#U5A Datasheet - Page 115

• Manufacturer Part Number: M30290FAHP#U5A
• Description: IC M16C/29 MCU FLASH 96K 80LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/Tiny/29r

Specifications of M30290FAHP#U5A

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 71
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 27x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 80-LQFP
• For Use With: R0K330290S000BE - KIT EVAL STARTER FOR M16C/29M30290T2-CPE - EMULATOR COMPACT M16C/26A/28/29M30290T2-CPE-HP - EMULATOR COMPACT FOR M16C/TINY
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

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10. Watchdog Timer
e
E
1
. v
J
Figure 10.1 Watchdog Timer Block Diagram
6
0
The watchdog timer is the function of detecting when the program is out of control. Therefore, we recommend
using the watchdog timer to improve reliability of a system. The watchdog timer contains a 15-bit counter which
counts down the clock derived by dividing the CPU clock using the prescaler. Whether to generate a watchdog
timer interrupt request or apply a watchdog timer reset as an operation to be performed when the watchdog timer
underflows after reaching the terminal count can be selected using the PM12 bit in the PM1 register. The PM12
bit can only be set to 1 (reset). Once this bit is set to 1, it cannot be set to 0 (watchdog timer interrupt) in a
program. Refer to 5.3 Watchdog Timer Reset for the details of watchdog timer reset.
When the main clock source is selected for CPU clock, on-chip oscillator clock, PLL clock, the WDC7 bit in the
WDC register value for prescaler can be chosen to be 16 or 128. If a sub-clock is selected for CPU clock, the
prescaler is always 2 no matter how the WDC7 bit is set. The period of watchdog timer can be calculated as
given below. The period of watchdog timer is, however, subject to an error due to the prescaler.
For example, when CPU clock is set to 16 MHz and the divide-by-N value for the prescale ris set to 16, the
watchdog timer period is approx. 32.8 ms.
The watchdog timer is initialized by writing to the WDTS register. The prescaler is initialized after reset. Note that
the watchdog timer and the prescaler both are inactive after reset, so that the watchdog timer is activated to start
counting by writing to the WDTS register.
Write the WDTS register with shorter cycle than the watchdog timer cycle. Set the WDTS register also in the
beginning of the watchdog timer interrupt routine.
In stop mode and wait mode, the watchdog timer and prescaler are stopped. Counting is resumed from the held
value when the modes or state are released.
Figure 10.1 shows the block diagram of the watchdog timer. Figure 10.2 shows the watchdog timer-related
registers.
1
9
C
With main clock source chosen for CPU clock, on-chip oscillator clock, PLL clock
Watchdog timer period =
With sub-clock chosen for CPU clock
Watchdog timer period =
1 .
B
2 /
Internal reset signal
(low active)
0
2
CPU clock
9
1
M
0
G
1
r a
0 -
o r
Write to WDTS register
3 .
1
u
, 0
1
p
2
2
0
0
7
page 89
On-chip oscillator clock
Prescaler
1/128
1/16
1/2
f o
Prescaler dividing (16 or 128) X Watchdog timer count (32768)
Prescaler dividing (2) X Watchdog timer count (32768)
4
5
8
CM07 = 0
WDC7 = 1
CM07 = 1
CM07 = 0
WDC7 = 0
PM22 = 0
PM22 = 1
CPU clock
CPU clock
Watchdog timer
Set to 7FFF
16
PM12 = 0
PM12 = 1
Reset
Watchdog timer
interrupt request