M30290FAHP#U5A Renesas Electronics America, M30290FAHP#U5A Datasheet - Page 150

• Manufacturer Part Number: M30290FAHP#U5A
• Description: IC M16C/29 MCU FLASH 96K 80LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/Tiny/29r

Specifications of M30290FAHP#U5A

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 71
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 27x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 80-LQFP
• For Use With: R0K330290S000BE - KIT EVAL STARTER FOR M16C/29M30290T2-CPE - EMULATOR COMPACT M16C/26A/28/29M30290T2-CPE-HP - EMULATOR COMPACT FOR M16C/TINY
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R
R
M
e
E
1
. v
J
Figure 12.24 TB2SC Register in A/D Trigger Mode
6
Figure 12.23 TBiMR Register in A/D Trigger Mode
0
C
1
9
1 .
B
2 /
0
2
9
1
M
0
G
1
r a
o r
0 -
NOTE:
Timer B2 special mode register
b7
NOTES:
Timer Bi Mode Register (i= 0 to 1)
3 .
b7
1
u
1. Write to this register after setting the PRC1 bit in the PRCR register to 1 (write enabled).
2. If the INV11 bit is 0 (three-phase mode 0) or the INV06 bit is 1 (triangular wave modulation mode), set this bit to 0 (timer
3. When setting the IVPCR1 bit to 1 (three-phase output forcible cutoff by SD pin input enabled), Set the PD8
4. Related pins are U(P8
5. When this bit is used in delayed trigger mode 0, set bits TB0EN and TB1EN to 1 (A/D trigger mode).
6. When setting the TB2SEL bit to 1 (underflow of TB2 interrupt generation frequency setting counter[ICTB2]), set the INV02
, 0
1. When this bit is used in delayed trigger mode 0, set the same count source to the timer B0 and timer B1.
b6
0 0
1
p
b6
B2 underflow).
mode).
and set the IVPCR1 bit to 0 after forcible cutoff, pins U, U, V, V, W, and W are exit from the high-impedance state. If a low-
level (“L”) signal is applied to the SD pin, three-phase motor control timer output will be disabled (INV03=0). At this time,
when the IVPCR1 bit is 0, pins U, U, V, V, W, and W become programmable I/O ports. When the IVPCR1 bit is set to 1,
pins U, U, V, V, W, and W are placed in a high-impedance state regardless of which function of those pins is used.
bit to 1 (three-phase motor control timer function).
2
2
b5
0
b5
0
b4
7
b4
b3
1 1
b3
b2
page 124
b2
b1
b1
0
b0
b0
0
0
), U(P8
Bit Symbol
TB2SEL
PWCON
IVPCR1
(b6-b5)
TB0EN
TB1EN
f o
Bit Symbol
(b7)
Symbol
TB2SC
TMOD0
TMOD1
TCK0
TCK1
4
MR0
MR1
MR2
MR3
1
), V(P7
Symbol
TB0MR to TB1MR
5
8
Three-phase output port
SD control bit 1
Timer B0 operation mode
select bit
Timer B1 operation mode
select bit
Timer B2 reload timing
switch bit
Trigger select bit
(1)
Reserved bits
Nothing is assigned. If necessary, set to 0.
When read, its content is 0
2
), V(P7
Operation mode select bit
When write in A/D trigger mode, set to 0. When read in A/D trigger
mode, its content is undefined
Invalid in A/D trigger mode
Either 0 or 1 is enabled
TB0MR register
Set to 0 in A/D trigger mode
TB1MR register
Nothing is assigned. If necessary, set to 0. When read, its
content is undefined
Count source select bit
Address
039E
Bit Name
3
), W(P7
(2)
16
(3, 4, 7)
Bit Name
(6)
4
), W(P7
Address
039B
5
0: TB2 interrupt
1: Underflow of TB2 interrupt
). When a high-level ("H") signal is applied to the SD pin
0: Timer B2 underflow
1: Timer A output at odd-numbered
0: Three-phase output forcible cutoff
1: Three-phase output forcible cutoff
0: Other than A/D trigger mode
1: A/D trigger mode
0: Other than A/D trigger mode
1: A/D trigger mode
16
X0000000
After Reset
Set to 0
(1)
generation frequency setting counter [ICTB2]
to 039C
by SD pin input (high impedance)
disabled
by SD pin input (high impedance)
enabled
0 0: Timer mode or A/D trigger mode
b7 b6
0 0: f
0 1: f
1 0: f
1 1: f
b1 b0
2
16
1
8
32
C32
or f
2
After Reset
00XX0000
Function
Function
(5)
(5)
2
5
bit to 0 (= input
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RO
RW
RW