MCF5208CAB166 Freescale Semiconductor, MCF5208CAB166 Datasheet - Page 40

• Manufacturer Part Number: MCF5208CAB166
• Description: MCU 32BIT 166.67MHZ 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF520xr

Specifications of MCF5208CAB166

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 166.67MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 50
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 166.67MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.8/2.5/3.3V
• Operating Supply Voltage (max): 1.6/1.95/2.75/3.6V
• Operating Supply Voltage (min): 1.4/1.7/2.25/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 160
• Package Type: PQFP
• Processor Series: MCF520x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Compliant

Electrical Characteristics
5.15 JTAG and Boundary Scan Timing
40
NOTES:
1
Num
J10
J11
J12
J13
J14
JTAG_EN is expected to be a static signal. Hence, specific timing is not associated with it.
J1
J2
J3
J4
J5
J6
J7
J8
J9
TCLK
(input)
TCLK Frequency of Operation
TCLK Cycle Period
TCLK Clock Pulse Width
TCLK Rise and Fall Times
Boundary Scan Input Data Setup Time to TCLK Rise
Boundary Scan Input Data Hold Time after TCLK Rise
TCLK Low to Boundary Scan Output Data Valid
TCLK Low to Boundary Scan Output High Z
TMS, TDI Input Data Setup Time to TCLK Rise
TMS, TDI Input Data Hold Time after TCLK Rise
TCLK Low to TDO Data Valid
TCLK Low to TDO High Z
TRST Assert Time
TRST Setup Time (Negation) to TCLK High
MCF5208 ColdFire
Characteristics
Table 24. JTAG and Boundary Scan Timing
J4
V
IH
Figure 28. Test Clock Input Timing
V
IL
1
®
Microprocessor Data Sheet, Rev. 3
J3
J4
J2
Symbol
t
t
t
t
t
t
t
t
TAPBHT
TRSTST
TAPBST
TRSTAT
BSDST
BSDHT
t
t
TDODV
TDODZ
f
t
t
t
BSDV
BSDZ
JCYC
JCYC
JCRF
JCW
J3
Min
100
DC
26
26
10
10
4
0
4
0
0
4
0
0
Freescale Semiconductor
Max
1/4
33
33
26
—
—
—
—
—
—
—
—
3
8
f
Unit
t
sys/2
CYC
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns