MCF5208CAB166 Freescale Semiconductor, MCF5208CAB166 Datasheet - Page 29

• Manufacturer Part Number: MCF5208CAB166
• Description: MCU 32BIT 166.67MHZ 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF520xr

Specifications of MCF5208CAB166

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 166.67MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 50
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 166.67MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.8/2.5/3.3V
• Operating Supply Voltage (max): 1.6/1.95/2.75/3.6V
• Operating Supply Voltage (min): 1.4/1.7/2.25/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 160
• Package Type: PQFP
• Processor Series: MCF520x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Compliant

NOTES:
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5.8.1
The following timing numbers indicate when data will be latched or driven onto the external bus, relative
to the memory bus clock, when operating in SDR mode on write cycles and relative to SD_DQS on read
cycles. The SDRAM controller is a DDR controller with an SDR mode. Because it is designed to support
DDR, a DQS pulse must remain supplied to the device for each data beat of an SDR read. The ColdFire
processor accomplishes this by asserting a signal called SD_SDR_DQS during read cycles. Take care
during board design to adhere to the following guidelines and specs with regard to the SD_SDR_DQS
signal and its usage.
Freescale Semiconductor
Symbol
The device supports the same frequency of operation for FlexBus and SDRAM as that of the internal bus clock. Please see the
PLL chapter of the MCF5208 Reference Manual for more information on setting the SDRAM clock rate.
SD_CLK is one SDRAM clock in (ns).
Pulse width high plus pulse width low cannot exceed min and max clock period.
SD_DQS is designed to pulse 0.25 clock before the rising edge of the memory clock. This is a guideline only. Subtle variation from
this guideline is expected. SD_DQS only pulses during a read cycle and one pulse occurs for each data beat.
SDR_DQS is designed to pulse 0.25 clock before the rising edge of the memory clock. This spec is a guideline only. Subtle
variation from this guideline is expected. SDR_DQS only pulses during a read cycle and one pulse occurs for each data beat.
The SDR_DQS pulse is designed to be 0.5 clock in width. The timing of the rising edge is most important. The falling edge does
not affect the memory controller.
Because a read cycle in SDR mode continues using the DQS circuit within the device, it is most critical that the data valid window
be centered 1/4 clk after the rising edge of DQS. Ensuring that this happens results in successful SDR reads. The input setup spec
is provided as guidance.
SD10
SD11
SD12
SD13
SD1
SD3
SD4
SD5
SD6
SD7
SD8
SD9
Frequency of Operation
Clock Period (t
Pulse Width High (t
Pulse Width Low (t
Address, SD_CKE, SD_CAS, SD_RAS, SD_WE,
SD_BA, SD_CS[1:0] - Output Valid (t
Address, SD_CKE, SD_CAS, SD_RAS, SD_WE,
SD_BA, SD_CS[1:0] - Output Hold (t
SD_SDR_DQS Output Valid (t
SD_DQS[3:2] input setup relative to SD_CLK (t
SD_DQS[3:2] input hold relative to SD_CLK (t
Data (D[31:0]) Input Setup relative to SD_CLK
(reference only) (t
Data Input Hold relative to SD_CLK (reference only)
(t
Data (D[31:0]) and Data Mask(SD_DQM[3:0]) Output
Valid (t
Data (D[31:0]) and Data Mask (SD_DQM[3:0]) Output
Hold (t
DIH
SDR SDRAM AC Timing Characteristics
)
DH
DV
)
)
CK
)
DIS
CKL
Characteristic
CKH
)
)
MCF5208 ColdFire
)
DQSOV
Table 12. SDR Timing Specifications
)
CMV
CMH
)
)
®
Microprocessor Data Sheet, Rev. 3
DQSIH
DQSIS
)
) t
t
t
t
t
t
DQVSDCH
SDCHDMV
Symbol
SDCHACV
t
SDCHDMI
DQISDCH
t
SDCHACI
t
t
t
DVSDCH
DISDCH
DQSOV
t
SDCKH
SDCKL
SDCK
0.25 × SD_CLK 0.40 × SD_CLK
0.25 × SD_CLK
Does not apply. 0.5 SD_CLK fixed width.
0.45
0.45
Min
2.0
1.0
1.5
60
12
—
—
—
0.75 × SD_CLK
0.5 × SD_CLK
Self timed
83.33
16.67
+ 1.0
+ 0.5
Electrical Characteristics
Max
0.55
0.55
—
—
—
—
SD_CLK
SD_CLK
MHz
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
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