R5F212A8SNFA#U0 Renesas Electronics America, R5F212A8SNFA#U0 Datasheet - Page 417

• Manufacturer Part Number: R5F212A8SNFA#U0
• Description: IC R8C/2A MCU FLASH 64K 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/2x/2Ar

Specifications of R5F212A8SNFA#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 55
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 5.5 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 64-LQFP
• For Use With: R0K5212D8S001BE - KIT STARTER FOR R8C/2DR0K5212D8S000BE - KIT DEV FOR R8C/2D
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/2A Group, R8C/2B Group
Rev.2.00
REJ09B0324-0200
16.2
Table 16.2
NOTE:
Transfer data format
Operating modes
Master/slave device
I/O pins
Transfer clocks
Receive error detection • Overrun error
Multimaster error
detection
Interrupt requests
Select functions
Clock synchronous serial I/O with chip select supports clock synchronous serial data communication.
Table 16.2 shows a Clock Synchronous Serial I/O with Chip Select Specifications and Figure 16.1 shows a Block
Diagram of Clock Synchronous Serial I/O with Chip Select. Figures 16.2 to 16.10 show clock synchronous serial
I/O with chip select associated registers.
1. Clock synchronous serial I/O with chip select has only one interrupt vector table.
Clock Synchronous Serial I/O with Chip Select (SSU)
Nov 26, 2007
Item
Clock Synchronous Serial I/O with Chip Select Specifications
Page 395 of 580
• Transfer data length: 8 bits
• Clock synchronous communication mode
• 4-wire bus communication mode (including bidirectional communication)
Selectable
SSCK (I/O): Clock I/O pin
SSI (I/O): Data I/O pin
SSO (I/O): Data I/O pin
SCS (I/O): Chip-select I/O pin
• When the MSS bit in the SSCRH register is set to 0 (operates as slave
• When the MSS bit in the SSCRH register is set to 1 (operates as master
• Clock polarity and phase of SSCK can be selected.
• Conflict error
5 interrupt requests (transmit-end, transmit-data-empty, receive-data-full,
overrun error, and conflict error)
• Data transfer direction
• SSCK clock polarity
• SSCK clock phase
device), external clock is selected (input from SSCK pin).
device), internal clock (selectable among f1/256, f1/128, f1/64, f1/32, f1/16,
f1/8 and f1/4, output from SSCK pin) is selected.
Continuous transmission and reception of serial data are supported since
both transmitter and receiver have buffer structures.
Overrun error occurs during reception and completes in error. While the
RDRF bit in the SSSR register is set to 1 (data in the SSRDR register) and
when next serial data receive is completed, the ORER bit is set to 1.
When the SSUMS bit in the SSMR2 register is set to 1 (4-wire bus
communication mode) and the MSS bit in the SSCRH register is set to 1
(operates as master device) and when starting a serial communication, the
CE bit in the SSSR register is set to 1 if “L” applies to the SCS pin input.
When the SSUMS bit in the SSMR2 register is set to 1 (4-wire bus
communication mode), the MSS bit in the SSCRH register is set to 0
(operates as slave device) and the SCS pin input changes state from “L” to
“H”, the CE bit in the SSSR register is set to 1.
Selects MSB-first or LSB-first
Selects “L” or “H” level when clock stops
Selects edge of data change and data download
(1)
Specification
.
16. Clock Synchronous Serial Interface