R5F212A8SNFA#U0 Renesas Electronics America, R5F212A8SNFA#U0 Datasheet - Page 252

• Manufacturer Part Number: R5F212A8SNFA#U0
• Description: IC R8C/2A MCU FLASH 64K 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/2x/2Ar

Specifications of R5F212A8SNFA#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 55
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 5.5 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 64-LQFP
• For Use With: R0K5212D8S001BE - KIT STARTER FOR R8C/2DR0K5212D8S000BE - KIT DEV FOR R8C/2D
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/2A Group, R8C/2B Group
Rev.2.00
REJ09B0324-0200
Table 14.23
j = A, B, C, or D
Count source
Count operation
PWM waveform
Count start conditions
Count stop conditions
Interrupt request
generation timing
TRCIOA/TRCTRG pin
function
TRCIOB pin function
TRCIOC and TRCIOD pin
functions
INT0 pin function
Read from timer
Write to timer
Select functions
Nov 26, 2007
Item
Specifications of PWM2 Mode
Page 230 of 580
f1, f2, f4, f8, f32, fOCO40M, or external signal (rising edge) input to TRCCLK pin
Increment TRC register
PWM period: 1/fk × (m + 1) (no TRCTRG input)
Active level width: 1/fk × (n - p)
Wait time from count start or trigger: 1/fk × (p + 1)
• Bits TCEG1 to TCEG0 in the TRCCR2 register are set to 00b (TRCTRG trigger
• Bits TCEG1 to TCEG0 in the TRCCR2 register are set to 01b, 10b, or 11b (TRCTRG
• 0 (count stops) is written to the TSTART bit in the TRCMR register while the CSEL bit in
• The count stops due to a compare match with TRCGRA while the CSEL bit in the
• Compare match (contents of TRC and TRCGRj registers match)
• The TRC register overflows
Programmable I/O port or TRCTRG input
PWM output
Programmable I/O port
Programmable I/O port, pulse output forced cutoff signal input, or INT0 interrupt input
The count value can be read by reading the TRC register.
The TRC register can be written to.
• External trigger and valid edge selected
• Buffer operation (Refer to 14.3.3.2 Buffer Operation.)
• Pulse output forced cutoff signal input (Refer to 14.3.3.4 Forced Cutoff of Pulse
• Digital filter (Refer to 14.3.3.3 Digital Filter.)
disabled) or the CSEL bit in the TRCCR2 register is set to 0 (count continues).
1 (count starts) is written to the TSTART bit in the TRCMR register.
trigger enabled) and the TSTART bit in the TRCMR register is set to 1 (count starts).
A trigger is input to the TRCTRG pin
the TRCCR2 register is set to 0 or 1.
The TRCIOB pin outputs the initial level in accordance with the value of the TOB bit in
the TRCCR1 register. The TRC register retains the value before count stops.
TRCCR2 register is set to 1
The TRCIOB pin outputs the initial level. The TRC register retains the value before
count stops if the CCLR bit in the TRCCR1 register is set to 0. The TRC register is set
to 0000h if the CCLR bit in the TRCCR1 register is set to 1.
The edge or edges of the signal input to the TRCTRG pin can be used as the PWM
output trigger: rising edge, falling edge, or both rising and falling edges
Output.)
fk: Count source frequency
m: TRCGRA register setting value
n: TRCGRB register setting value
p: TRCGRC register setting value
TRCIOB output
TRCTRG input
m+1
n+1
p+1
n-p
Specification
(TRCTRG: Rising edge, active level is “H”)
n+1
p+1
n-p
14. Timers