R5F212A8SNFA#U0 Renesas Electronics America, R5F212A8SNFA#U0 Datasheet - Page 256
R5F212A8SNFA#U0
Manufacturer Part Number
R5F212A8SNFA#U0
Description
IC R8C/2A MCU FLASH 64K 64-LQFP
Manufacturer
Renesas Electronics America
Series
R8C/2x/2Ar
Specifications of R5F212A8SNFA#U0
Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
POR, PWM, Voltage Detect, WDT
Number Of I /o
55
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
3K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 5.5 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
64-LQFP
For Use With
R0K5212D8S001BE - KIT STARTER FOR R8C/2DR0K5212D8S000BE - KIT DEV FOR R8C/2D
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5F212A8SNFA#U0R5F212A8SNFA#V2
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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R8C/2A Group, R8C/2B Group
Rev.2.00
REJ09B0324-0200
Figure 14.60
• TRCGRB register setting value greater than TRCGRA
register setting value
TRCMR register
TRCSR register
TRCSR register
TRCSR register
TRCIOB output
TSTART bit in
The above applies under the following conditions:
• The TOB bit in the TRCCR1 register is set to 0 (initial level is “L”, “H” output at compare match with the TRCGRC register, “L” output at compare
• Bits TCEG1 and TCEG0 in the TRCCR2 register are set to 00b (TRCTRG trigger input disabled).
IMFC bit in
IMFA bit in
IMFB bit in
match with the TRCGRB register).
Nov 26, 2007
TRC register value
0000h
Operating Example of PWM2 Mode (Duty 0% and Duty 100%)
1
0
1
0
1
0
1
0
n
m
p
“L” initial
output
m+1
p+1
Page 234 of 580
“H” output at TRCGRC register
compare match
Set to 0 by a
program
No compare match with
TRCGRB register, so
“H” output continues
• TRCGRC register setting value greater than TRCGRA
TRCMR register
TRCSR register
TRCSR register
TRCSR register
TRCIOB output
register setting value
TSTART bit in
IMFA bit in
IMFB bit in
IMFC bit in
m: TRCGRA register setting value
n: TRCGRB register setting value
p: TRCGRC register setting value
TRC register value
0000h
1
0
1
0
1
0
1
0
No compare match
with TRCGRC register,
so “L” output continues
p
m
n
“L” initial
output
m+1
n+1
“L” output at
TRCGRB register
compare match
with no change.
14. Timers
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