R5F212A8SNFA#U0 Renesas Electronics America, R5F212A8SNFA#U0 Datasheet - Page 310

• Manufacturer Part Number: R5F212A8SNFA#U0
• Description: IC R8C/2A MCU FLASH 64K 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/2x/2Ar

Specifications of R5F212A8SNFA#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 55
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 5.5 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 64-LQFP
• For Use With: R0K5212D8S001BE - KIT STARTER FOR R8C/2DR0K5212D8S000BE - KIT DEV FOR R8C/2D
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/2A Group, R8C/2B Group
Rev.2.00
REJ09B0324-0200
Figure 14.106 Registers TRDOCR and TRDCR0 to TRDCR1 in PWM Mode
Timer RD Control Register i (i = 0 or 1)
Timer RD Output Control Register
b7 b6 b5 b4
NOTES:
b7 b6 b5 b4
NOTES:
0 0 1
1.
2.
1.
2.
This setting is enabled w hen the STCLK bit in the TRDFCR register is set to 1 (external clock input enabled).
Bits CKEG1 to CKEG0 are enabled w hen bits TCK2 to TCK0 are set to 101b (TRDCLK input) and the STCLK bit in the
TRDFCR register is set to 1 (external clock input enabled).
Write to the TRDOCR register w hen both the TSTART0 and TSTART1 bits in the TRDSTR register are set to 0 (count
stops).
If the pin function is set for w aveform output (refer to Tables 14.28 to 14.30 and Tables 14.32 to 14.34 ), the initial
output level is output w hen the TRDOCR register is set.
Nov 26, 2007
0
b3 b2
b3 b2
b1 b0
b1 b0
0
Bit Symbol
Bit Symbol
TRDOCR
TRDCR0
TRDCR1
Symbol
CKEG0
CKEG1
CCLR0
CCLR1
CCLR2
Symbol
TOA0
TOB0
TOC0
TOD0
TOA1
TOB1
TOC1
TOD1
TCK0
TCK1
TCK2
Page 288 of 580
Count source select bits
External clock edge select bits
TRDi counter clear select bits
TRDIOA0 output level select bit
TRDIOB0 output level select bit
TRDIOC0 initial output level select bit
TRDIOD0 initial output level select bit
TRDIOA1 initial output level select bit
TRDIOB1 initial output level select bit
TRDIOC1 initial output level select bit
TRDIOD1 initial output level select bit
(1)
Address
Bit Name
0140h
0150h
Address
Bit Name
013Dh
(2)
(2)
b2 b1 b0
0 0 0 : f1
0 0 1 : f2
0 1 0 : f4
0 1 1 : f8
1 0 0 : f32
1 0 1 : TRDCLK input
1 1 0 : fOCO40M
1 1 1 : Do not set.
b4 b3
0 0 : Count at the rising edge
0 1 : Count at the falling edge
1 0 : Count at both edges
1 1 : Do not set.
Set to 001b (the TRDi register cleared at
compare match w ith TRDGRAi register) in PWM
mode.
(2)
(2)
(2)
(2)
(2)
Set this bit to 0 (enable output) in
PWM mode.
0 : Initial output is inactive
1 : Initial output is active level
Set this bit to 0 (enable output) in
PWM mode.
0 : Inactive level
1 : Active level
level
After Reset
Function
(1)
00h
00h
After Reset
Function
00h
14. Timers
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW