MC56F8011VFAE Freescale Semiconductor, MC56F8011VFAE Datasheet - Page 77

• Manufacturer Part Number: MC56F8011VFAE
• Description: IC DIGITAL SIGNAL CTLR 32-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8011VFAE

• Core Processor: 56800
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 26
• Program Memory Size: 12KB (6K x 16)
• Program Memory Type: FLASH
• Ram Size: 1K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 6x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 32-LQFP
• Product: DSCs
• Data Bus Width: 16 bit
• Processor Series: MC56F80xx
• Core: 56800E
• Numeric And Arithmetic Format: Fixed-Point
• Device Million Instructions Per Second: 32 MIPs
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 26
• Data Ram Size: 2 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MC56F8037EVM, DEMO56F8014-EE, DEMO56F8013-EE
• Interface Type: SCI, SPI, I2C
• Minimum Operating Temperature: - 40 C
• For Use With: CPA56F8013 - BOARD SOCKET FOR MC56F8013APMOTOR56F8000E - KIT DEMO MOTOR CTRL SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

6.3.9.4
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
6.3.9.5
6.3.9.6
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
6.3.9.7
6.3.9.8
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
6.3.9.9
6.3.9.10
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
6.3.9.11
6.3.10
The I/O Short Address Location registers are used to specify the memory referenced via the I/O short
address mode. The I/O short address mode allows the instruction to specify the lower six bits of address;
the upper address bits are not directly controllable. This register set allows limited control of the full
address, as shown in
Freescale Semiconductor
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0 = The clock is not provided to the Quad Timer module(the Quad Timer module is disabled)
1 = Clocks to the Quad Timer module are enabled
0 = The clock is not provided to the SCI module (the SCI module is disabled)
1 = Clocks to the SCI module are enabled
0 = The clock is not provided to the SPI module (the SPI module is disabled)
1 = Clocks to the SPI module are enabled
0 = The clock is not provided to the PWM module (the PWM module is disabled)
1 = Clocks to the PWM module are enabled
I/O Short Address Location Register (SIM_IOSAHI and
SIM_IOSALO)
Reserved—Bits 12–7
Timer Clock Enable (TMR)—Bit 6
Reserved—Bit 5
SCI Clock Enable (SCI)—Bit 4
Reserved—Bit 3
SPI Clock Enable (SPI)—Bit 2
Reserved—Bit 1
PWM Clock Enable (PWM)—Bit 0
Figure
6-12.
56F8013/56F8011 Data Sheet, Rev. 12
Register Descriptions
77