MC56F8011VFAE Freescale Semiconductor, MC56F8011VFAE Datasheet - Page 63

• Manufacturer Part Number: MC56F8011VFAE
• Description: IC DIGITAL SIGNAL CTLR 32-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8011VFAE

• Core Processor: 56800
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 26
• Program Memory Size: 12KB (6K x 16)
• Program Memory Type: FLASH
• Ram Size: 1K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 6x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 32-LQFP
• Product: DSCs
• Data Bus Width: 16 bit
• Processor Series: MC56F80xx
• Core: 56800E
• Numeric And Arithmetic Format: Fixed-Point
• Device Million Instructions Per Second: 32 MIPs
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 26
• Data Ram Size: 2 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MC56F8037EVM, DEMO56F8014-EE, DEMO56F8013-EE
• Interface Type: SCI, SPI, I2C
• Minimum Operating Temperature: - 40 C
• For Use With: CPA56F8013 - BOARD SOCKET FOR MC56F8013APMOTOR56F8000E - KIT DEMO MOTOR CTRL SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Note:
5.5.16.4
This bit allows all interrupts to be disabled.
5.5.16.5
This bit field is reserved or not implemented. It is read as 1 and cannot be modified by writing.
5.5.16.6
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
5.6 Resets
5.6.1
5.6.2
5.6.2.1
The ITCN provides the 56800E core with a reset vector address on the VAB pins whenever RESET is
asserted from the SIM. The reset vector will be presented until the second rising clock edge after RESET
is released. The general timing is shown in
Freescale Semiconductor
•
•
0 = Normal operation (default)
1 = All interrupts disabled
RES
CLK
Nested interrupts may cause this field to be updated before the original interrupt service routine can
read it.
General
Description of Reset Operation
VAB
PAB
Core Reset
Interrupt Disable (INT_DIS)—Bit 5
Reserved—Bits 4–2
Reserved—Bits 1–0
Reset Handshake Timing
Reset
Priority
56F8013/56F8011 Data Sheet, Rev. 12
Figure 5-19 Reset Interface
Table 5-4 Reset Summary
Figure
5-19.
RESET_VECTOR_ADR
Source
RST
Core reset from the SIM
Characteristics
READ_ADR
Resets
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