MC56F8011VFAE Freescale Semiconductor, MC56F8011VFAE Datasheet - Page 67

• Manufacturer Part Number: MC56F8011VFAE
• Description: IC DIGITAL SIGNAL CTLR 32-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8011VFAE

• Core Processor: 56800
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 26
• Program Memory Size: 12KB (6K x 16)
• Program Memory Type: FLASH
• Ram Size: 1K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 6x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 32-LQFP
• Product: DSCs
• Data Bus Width: 16 bit
• Processor Series: MC56F80xx
• Core: 56800E
• Numeric And Arithmetic Format: Fixed-Point
• Device Million Instructions Per Second: 32 MIPs
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 26
• Data Ram Size: 2 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MC56F8037EVM, DEMO56F8014-EE, DEMO56F8013-EE
• Interface Type: SCI, SPI, I2C
• Minimum Operating Temperature: - 40 C
• For Use With: CPA56F8013 - BOARD SOCKET FOR MC56F8013APMOTOR56F8000E - KIT DEMO MOTOR CTRL SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

6.3.1
6.3.1.1
This bit enables the operation of the Timer Channel 3 peripheral clock in Stop mode.
Freescale Semiconductor
•
Offset
Add.
$C
$D
$0
$1
$2
$3
$4
$5
$6
$7
$8
$A
$B
$E
Base + $0
0 = Timer Channel 3 disabled in Stop mode
RESET
Write
Read
SIM_IOSALO
SIM_IOSAHI
SIM_MSHID
SIM_SWC0
SIM_SWC1
SIM_SWC2
SIM_SWC3
SIM_LSHID
SIM_PWR
SIM_GPS
SIM_PCE
Acronym
Reserved
CLKOUT
Address
RSTAT
SIM Control Register (SIM_CTRL)
CTRL
SIM_
SIM_
SIM_
Timer Channel 3 Stop Disable (TC3_SD)—Bit 15
TC3_
SD
W
W
W
W
W
W
W
W
W
W
W
W
W
W
15
R
R
R
R
R
R
R
R
R
R
R
R
R
R
0
TC3_
TCR
SD
I2C
15
0
0
0
0
0
0
0
TC2_
14
SD
0
= Read as 0
= Reserved
Figure 6-2 SIM Control Register (SIM_CTRL)
TC2_
PCR
SD
14
0
0
1
0
0
0
0
TC1_
SD
13
Figure 6-1 SIM Register Map Summary
0
TC1_
ADC
SD
13
0
0
0
0
0
0
0
TC0_
SD
12
0
56F8013/56F8011 Data Sheet, Rev. 12
TC0_
SD
12
0
0
0
0
0
0
0
0
SCI_
11
SD
0
CFG_
SCI_
SD
11
B7
0
0
0
0
0
0
0
1
10
0
0
=
= Reserved
CFG_
Read as 1
10
B6
0
0
0
0
0
0
0
0
TC3_
INP
9
0
PWM3 PWM2 PWM1 PWM0
CFG_
TC3_
INP
B5
9
0
0
0
0
0
0
Software Control Data 0
Software Control Data 1
Software Control Data 2
Software Control Data 3
8
0
0
CFG_
B4
8
ISAL[21:6]
0
0
1
0
0
0
0
7
0
0
CFG_
B3
7
0
0
1
0
0
0
0
6
0
0
CFG_
TMR
B2
6
0
0
1
0
0
0
ONCE
EBL
5
0
ONCE
CFG_
EBL0
SWR
CLK
DIS
B1
5
1
0
0
0
0
RST
SW
4
0
COPR EXTR
CFG_
RST
SW
SCI
B0
4
1
1
0
0
3
DISABLE
0
STOP_
3
DISABLE
0
1
0
0
0
CFG_A5
STOP_
CLKOSEL
POR
2
0
SPI
2
0
1
0
0
Register Descriptions
ISAL[23:22]
1
DISABLE
0
LRSTDBY
1
DISABLE
0
1
0
0
CFG_A4
WAIT_
WAIT_
PWM
0
0
0
0
1
0
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