MC56F8011VFAE Freescale Semiconductor, MC56F8011VFAE Datasheet - Page 69

• Manufacturer Part Number: MC56F8011VFAE
• Description: IC DIGITAL SIGNAL CTLR 32-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8011VFAE

• Core Processor: 56800
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 26
• Program Memory Size: 12KB (6K x 16)
• Program Memory Type: FLASH
• Ram Size: 1K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 6x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 32-LQFP
• Product: DSCs
• Data Bus Width: 16 bit
• Processor Series: MC56F80xx
• Core: 56800E
• Numeric And Arithmetic Format: Fixed-Point
• Device Million Instructions Per Second: 32 MIPs
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 26
• Data Ram Size: 2 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MC56F8037EVM, DEMO56F8014-EE, DEMO56F8013-EE
• Interface Type: SCI, SPI, I2C
• Minimum Operating Temperature: - 40 C
• For Use With: CPA56F8013 - BOARD SOCKET FOR MC56F8013APMOTOR56F8000E - KIT DEMO MOTOR CTRL SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

6.3.1.11
6.3.1.12
6.3.2
This register is updated upon any system reset and indicates the cause of the most recent reset. It also
controls whether the COP reset vector or regular reset vector in the vector table is used. This register is
asynchronously reset during Power-On Reset (see power supervisor module) and subsequently is
synchronously updated based on the level of the external reset, software reset, or cop reset inputs. Only
one source will ever be indicated. In the event that multiple reset sources assert simultaneously, the
highest-precedence source will be indicated. The precedence from highest to lowest is POR, EXTR,
COPR, and SWR. While POR is always set during a Power-On Reset, EXTR will become set if the
external reset pin is asserted or remains asserted after the Power-On Reset (POR) has deasserted.
6.3.2.1
This bit field is reserved or not implemented. It is read as zero and cannot be modified by writing.
6.3.2.2
When set, this bit indicates that the previous system reset occurred as a result of a software reset (written
1 to SWRST bit in the SIM_CTRL register). It will not be set if a COP, external, or POR reset also
occurred.
6.3.2.3
When set, this bit indicates that the previous system reset was caused by the Computer Operating Properly
Freescale Semiconductor
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Base + $1
RESET
00 = Stop mode will be entered when the 56800E core executes a STOP instruction
01 = The 56800E STOP instruction will not cause entry into Stop mode
10 = Stop mode will be entered when the 56800E core executes a STOP instruction and the
STOP_DISABLE field is write-protected until the next reset
11 = The 56800E STOP instruction will not cause entry into Stop mode and the STOP_DISABLE field is
write-protected until the next reset
00 = Wait mode will be entered when the 56800E core executes a WAIT instruction
01 = The 56800E WAIT instruction will not cause entry into Wait mode
10 = Wait mode will be entered when the 56800E core executes a WAIT instruction and the
WAIT_DISABLE field is write-protected until the next reset
11 = The 56800E WAIT instruction will not cause entry into Wait mode and the WAIT_DISABLE field is
write-protected until the next reset
Read
Write
SIM Reset Status Register (SIM_RSTAT)
Stop Disable (STOP_DISABLE[1:0])—Bits 3–2
Wait Disable (WAIT_DISABLE[1:0])—Bits 1–0
Reserved—Bits 15–6
Software Reset (SWR)—Bit 5
COP Reset (COPR)—Bit 4
15
0
0
Figure 6-3 SIM Reset Status Register (SIM_RSTAT)
14
0
0
13
0
0
12
0
0
56F8013/56F8011 Data Sheet, Rev. 12
11
0
0
10
0
0
9
0
0
8
0
0
7
0
0
6
0
0
SWR
5
COPR
4
EXTR
3
POR
Register Descriptions
2
1
0
0
0
0
0
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