MC56F8011VFAE Freescale Semiconductor, MC56F8011VFAE Datasheet - Page 44

• Manufacturer Part Number: MC56F8011VFAE
• Description: IC DIGITAL SIGNAL CTLR 32-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8011VFAE

• Core Processor: 56800
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 26
• Program Memory Size: 12KB (6K x 16)
• Program Memory Type: FLASH
• Ram Size: 1K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 6x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 32-LQFP
• Product: DSCs
• Data Bus Width: 16 bit
• Processor Series: MC56F80xx
• Core: 56800E
• Numeric And Arithmetic Format: Fixed-Point
• Device Million Instructions Per Second: 32 MIPs
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 26
• Data Ram Size: 2 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MC56F8037EVM, DEMO56F8014-EE, DEMO56F8013-EE
• Interface Type: SCI, SPI, I2C
• Minimum Operating Temperature: - 40 C
• For Use With: CPA56F8013 - BOARD SOCKET FOR MC56F8013APMOTOR56F8000E - KIT DEMO MOTOR CTRL SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Part 5 Interrupt Controller (ITCN)
5.1 Introduction
The Interrupt Controller (ITCN) module is used to arbitrate between various interrupt requests (IRQs), to
signal to the 56800E core when an interrupt of sufficient priority exists, and to what address to jump in
order to service this interrupt.
5.2 Features
The ITCN module design includes these distinctive features:
For further information, see
5.3 Functional Description
The Interrupt Controller contains registers that allow each of the 46 interrupt sources to be set to one of
four priority levels (excluding certain interrupts that are of fixed priority). All of the interrupt requests of
a given level are priority encoded to determine the lowest numerical value of the active interrupt requests
for that level. Within a given priority level, number 0 is the highest priority and number 45 is the lowest.
During Wait and Stop modes, the system clocks and the 56800E core are turned off. The ITCN can wake
up the core and restart system clocks by signaling a pending IRQ to the System Integration Module (SIM)
to restart the clocks and service the IRQ. An IRQ can only wake up the core if the IRQ is enabled prior to
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•
•
•
Programmable priority levels for each IRQ
Two programmable Fast Interrupts
Notification to SIM module to restart clocks out of Wait and Stop modes
Ability to drive initial address on the address bus after reset
FM_CMD
FM_DATA
FM_OPT1
FM_TSTSIG
Register Acronym
Table 4-24 Flash Module Registers Address Map (Continued)
Table
Address Offset
4-2, Interrupt Vector Table Contents.
56F8013/56F8011 Data Sheet, Rev. 12
$1A
$1B
$1D
$14
$15
$16
$17
$18
$19
(FM_BASE = $00 F400)
Command Register
Reserved
Reserved
Reserved
Data Buffer Register
Reserved
Reserved
Optional Data 1 Register
Reserved
Test Array Signature Register
Register Description
Freescale Semiconductor