ST72F521AR9TC STMicroelectronics, ST72F521AR9TC Datasheet - Page 24
![IC MCU 8BIT 60K FLASH 64-TQFP](/photos/6/76/67655/497-64-tqfp_sml.jpg)
ST72F521AR9TC
Manufacturer Part Number
ST72F521AR9TC
Description
IC MCU 8BIT 60K FLASH 64-TQFP
Manufacturer
STMicroelectronics
Series
ST7r
Datasheet
1.ST72F521M9T6.pdf
(215 pages)
Specifications of ST72F521AR9TC
Core Processor
ST7
Core Size
8-Bit
Speed
8MHz
Connectivity
CAN, I²C, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
48
Program Memory Size
60KB (60K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3.8 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
64-TQFP, 64-VQFP
For Use With
497-6453 - BOARD EVAL BASED ON ST7LNBX
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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ST72F521, ST72521B
6 SUPPLY, RESET AND CLOCK MANAGEMENT
The device includes a range of utility features for
securing the application in critical situations (for
example in case of a power brown-out), and re-
ducing the number of external components. An
overview is shown in
For more details, refer to dedicated parametric
section.
Main features
■
■
■
■
Figure 11. Clock, Reset and Supply Block Diagram
24/215
– 5 Crystal/Ceramic resonator oscillators
– 1 Internal RC oscillator
– Main supply Low voltage detection (LVD)
– Auxiliary Voltage detector (AVD) with interrupt
Optional PLL for multiplying the frequency by 2
(not to be used with internal RC oscillator)
Reset Sequence Manager (RSM)
Multi-Oscillator Clock Management (MO)
System Integrity Management (SI)
RESET
OSC2
OSC1
capability for monitoring the main supply or
the EVD pin
V
V
EVD
SS
DD
Figure
OSCILLATOR
RESET SEQUENCE
MULTI-
(MO)
MANAGER
(RSM)
11.
f
OSC
(option)
PLL
SICSR
AVD AVD AVD LVD
S
SYSTEM INTEGRITY MANAGEMENT
0
1
IE
6.1 PHASE LOCKED LOOP
If the clock frequency input to the PLL is in the
range 2 to 4 MHz, the PLL can be used to multiply
the frequency by two to obtain an f
MHz. The PLL is enabled by option byte. If the PLL
is disabled, then f
Caution: The PLL is not recommended for appli-
cations where timing accuracy is required. See
“PLL Characteristics” on page 177.
Figure 10. PLL Block Diagram
f
OSC
AVD Interrupt Request
AUXILIARY VOLTAGE
F
LOW VOLTAGE
RF
DETECTOR
DETECTOR
(LVD)
(AVD)
0
PLL x 2
0
/ 2
OSC2 =
0
WDG
f
RF
OSC2
f
OSC
PLL OPTION BIT
/2.
CLOCK (MCC/RTC)
WITH REALTIME
0
1
TIMER (WDG)
CONTROLLER
MAIN CLOCK
WATCHDOG
OSC2
f
OSC2
of 4 to 8
f
CPU
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