ST72F521AR9TC STMicroelectronics, ST72F521AR9TC Datasheet - Page 137

• Manufacturer Part Number: ST72F521AR9TC
• Description: IC MCU 8BIT 60K FLASH 64-TQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72F521AR9TC

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: CAN, I²C, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 48
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3.8 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 64-TQFP, 64-VQFP
• For Use With: 497-6453 - BOARD EVAL BASED ON ST7LNBX
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

CONTROLLER AREA NETWORK (Cont’d)
INTERRUPT CONTROL REGISTER (ICR)
Read/Write
Reset Value: 00h
Bit 7 = Reserved.
Bit 6 = ESCI Extended Status Change Interrupt
−
Set by software to specify that SCIF is to be set on
receive errors also.
Cleared by software to set SCIF only on status
changes and wake-up but not on all receive errors.
Bit 5 = RXIE Receive Interrupt Enable
−
Set by software to enable an interrupt request
whenever a message has been received free of er-
rors.
Cleared by software to disable receive interrupt re-
quests.
Bit 4 = TXIE Transmit Interrupt Enable
−
Set by software to enable an interrupt request
Read/Set/Clear
Read/Set/Clear
Read/Set/Clear
7
0
ESCI
RXIE
TXIE
SCIE
ORIE
TEIE
0
0
whenever a message has been successfully trans-
mitted.
Cleared by software to disable transmit interrupt
requests.
Bit 3 = SCIE Status Change Interrupt Enable
−
Set by software to enable an interrupt request
whenever the node’s status changes in run mode or
whenever a dominant pulse is received in standby
mode.
Cleared by software to disable status change inter-
rupt requests.
Bit 2 = ORIE Overrun Interrupt Enable
−
Set by software to enable an interrupt request
whenever a message should be stored and no re-
ceive buffer is avalaible.
Cleared by software to disable overrun interrupt re-
quests.
Bit 1 = TEIE Transmit Error Interrupt Enable
−
Set by software to enable an interrupt whenever an
error has been detected during transmission of a
message.
Cleared by software to disable transmit error inter-
rupts.
Bit 0 = Reserved.
Read/Set/Clear
Read/Set/Clear
Read/Set/Clear
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