ST72F521AR9TC STMicroelectronics, ST72F521AR9TC Datasheet - Page 189

• Manufacturer Part Number: ST72F521AR9TC
• Description: IC MCU 8BIT 60K FLASH 64-TQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72F521AR9TC

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: CAN, I²C, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 48
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3.8 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 64-TQFP, 64-VQFP
• For Use With: 497-6453 - BOARD EVAL BASED ON ST7LNBX
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

12.11 COMMUNICATION INTERFACE CHARACTERISTICS
12.11.1 SPI - Serial Peripheral Interface
Subject to general operating conditions for V
f
Figure 106. SPI Slave Timing Diagram with CPHA=0
Notes:
1. Data based on design simulation and/or characterisation results, not tested in production.
2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has
its alternate function capability released. In this case, the pin status depends on the I/O port configuration.
3. Measurement points are done at CMOS levels: 0.3xV
CPU
Symbol
1/t
t
t
w(SCKH)
w(SCKL)
t
t
t
t
t
t
t
t
dis(SO)
t
t
t
t
r(SCK)
su(SS)
f(SCK)
t
su(MI)
t
v(MO)
h(MO)
f
su(SI)
a(SO)
v(SO)
h(SO)
MISO
MOSI
h(SS)
h(MI)
, and T
c(SCK)
h(SI)
SCK
SS
CPHA=0
CPOL=0
CPHA=0
CPOL=1
OUTPUT
INPUT
INPUT
A
SPI clock frequency
SPI clock rise and fall time
SS setup time
SS hold time
SCK high and low time
Data input setup time
Data input hold time
Data output access time
Data output disable time
Data output valid time
Data output hold time
Data output valid time
Data output hold time
unless otherwise specified.
see note 2
t
a(SO)
t
su(SS)
t
su(SI)
Parameter
t
t
MSB IN
w(SCKH)
w(SCKL)
MSB OUT
t
t
h(SI)
c(SCK)
t
DD
v(SO)
DD
Slave
,
Master
Slave
Slave
Slave
Master
Slave
Master
Slave
Master
Slave
Slave
Slave (after enable edge)
Master (before capture edge)
BIT6 OUT
and 0.7xV
Refer to I/O port characteristics for more details on
the input/output alternate function characteristics
(SS, SCK, MOSI, MISO).
3)
Conditions
DD
BIT1 IN
.
t
f
f
h(SO)
CPU
CPU
=8MHz
=8MHz
t
t
r(SCK)
f(SCK)
f
ST72F521, ST72521B
CPU
LSB IN
0.0625
see I/O port pin description
0.25
0.25
Min
120
120
100
100
100
100
100
90
LSB OUT
0
0
0
/128
t
h(SS)
f
f
CPU
CPU
Max
120
240
90
2
4
/4
/2
t
dis(SO)
189/215
Unit
t
MHz
CPU
ns
note 2
see