ST7FDALIF2M6TR STMicroelectronics, ST7FDALIF2M6TR Datasheet - Page 81

• Manufacturer Part Number: ST7FDALIF2M6TR
• Description: IC MCU 8BIT 8K FLASH 20-SOIC
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST7FDALIF2M6TR

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: DALI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 15
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 5.5 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-SOIC (7.5mm Width)
• Processor Series: ST7DALI
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 384 B
• Interface Type: DALI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 15
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST7FLITE-SK/RAIS, ST7DALI-EVAL, ST7MDT10-DVP3, ST7MDT10-EMU3, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 7 Channel / 13 bit, 7 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ST7DALIF2
14.6.10
14.6.11
14.6.12
PWMx duty cycle register low (DCRxL)
Read / Write
Reset Value: 0000 0000 (00h)
Bits 15:12 = Reserved.
Bits 11:0 = DCR[11:0] PWMx Duty Cycle Value
This 12-bit value is written by software. It defines the duty cycle of the corresponding PWM
output signal (see
In PWM mode (OEx=1 in the PWMCR register) the DCR[11:0] bits define the duty cycle of
the PWMx output signal (see
be compared with the 12-bit upcounter value.
Input capture register high (ATICRH)
Read only
Reset Value: 0000 0000 (00h)
Input capture register low (ATICRL)
Read only
Reset Value: 0000 0000 (00h)
Bits 15:12 = Reserved.
Bits 11:0 = ICR[11:0] Input Capture Data.
This is a 12-bit register which is readable by software and cleared by hardware after a reset.
The ATICR register contains captured the value of the 12-bit CNTR register when a rising or
falling edge occurs on the ATIC pin. Capture will only be performed when the ICF flag is
cleared.
DCR7
ICR7
15
7
0
7
DCR6
ICR6
0
Figure
35).
DCR5
ICR5
0
Figure
35). In Output Compare mode, they define the value to
DCR4
ICR4
0
DCR3
ICR11
ICR3
12-bit autoreload timer 2 (AT2)
DCR2
ICR10
ICR2
DCR1
ICR9
ICR1
DCR0
ICR8
ICR0
0
8
0
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