ST7FDALIF2M6TR STMicroelectronics, ST7FDALIF2M6TR Datasheet - Page 77
![IC MCU 8BIT 8K FLASH 20-SOIC](/photos/6/56/65691/497-20-soic__7_5mm_width__series_sml.jpg)
ST7FDALIF2M6TR
Manufacturer Part Number
ST7FDALIF2M6TR
Description
IC MCU 8BIT 8K FLASH 20-SOIC
Manufacturer
STMicroelectronics
Series
ST7r
Datasheet
1.ST7DALI-EVAL.pdf
(171 pages)
Specifications of ST7FDALIF2M6TR
Core Processor
ST7
Core Size
8-Bit
Speed
8MHz
Connectivity
DALI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
15
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
384 x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 5.5 V
Data Converters
A/D 7x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-SOIC (7.5mm Width)
Processor Series
ST7DALI
Core
ST7
Data Bus Width
8 bit
Data Ram Size
384 B
Interface Type
DALI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
15
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
ST7FLITE-SK/RAIS, ST7DALI-EVAL, ST7MDT10-DVP3, ST7MDT10-EMU3, STX-RLINK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 7 Channel / 13 bit, 7 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ST7FDALIF2M6TR
Manufacturer:
NEC
Quantity:
670
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ST7DALIF2
14.4
14.5
14.6
14.6.1
Low power modes
Table 36.
Interrupts
Table 37.
1. The CMP and IC events are connected to the same interrupt vector. The OVF event is mapped on a
2. Only if CK0=1 and CK1=0 (f
Register description
Timer control status register (ATCSR)
Read / Write
Reset Value: 0x00 0000 (x0h)
Bit 7 = Reserved.
Bit 6 = ICF Input Capture Flag.
This bit is set by hardware and cleared by software by reading the ATICR register (a read
access to ATICRH or ATICRL will clear this flag). Writing to this bit does not change the bit
value.
0: No input capture
1: An input capture has occurred
Bit 5 = ICIE IC Interrupt Enable.
This bit is set and cleared by software.
0: Input capture interrupt disabled
1: Input capture interrupt enabled
Slow
Wait
Active-halt
Halt
Overflow event
IC event
CMP event
separate vector (see
ATCSR register and the interrupt mask in the CC register is reset (RIM instruction).
Interrupt event
7
0
Mode
Effect of low power modes on AT2 timer
AT2 timer interrupt control bits
ICF
6
(1)
Table 15: Interrupt
COUNTER
ICIE
CMPF0
Event
OVF
flag
ICF
The input frequency is divided by 32
No effect on AT timer
AT timer halted except if CK0=1, CK1=0 and OVFIE=1
AT timer halted
= f
mapping). They generate an interrupt if the enable bit is set in the
LTIMER
CK1
)
control
Enable
CMPIE
OVIE
ICIE
bit
CK0
Description
from
Wait
Exit
Yes
Yes
Yes
12-bit autoreload timer 2 (AT2)
OVF
from
Halt
Exit
No
No
No
OVFIE
Active-halt
Yes
from
CMPIE
Exit
No
No
(2)
0
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