ST7FDALIF2M6TR STMicroelectronics, ST7FDALIF2M6TR Datasheet
ST7FDALIF2M6TR
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ST7FDALIF2M6TR Summary of contents
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MCU family with single voltage Flash memory, Features ■ Memories – 8 Kbytes single voltage Flash Program memory with readout protection, In-Circuit Programming and In-Application programming (ICP and IAP). 10K write/erase cycles guaranteed, data retention: 20 years at 55°C. ...
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Contents Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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ST7DALIF2 8 Central processing unit (CPU 8.1 ...
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Contents 10.4.1 10.4.2 11 Power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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ST7DALIF2 14 12-bit autoreload timer 2 (AT2 ...
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Contents 15.6.2 15.6.3 15.6.4 15.6.5 16 DALI communication module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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ST7DALIF2 17.4.4 17.4.5 17.4.6 17.5 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Contents 19.2 Instruction groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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ST7DALIF2 22.1.1 22.1.2 22.2 Device ordering information and transfer of customer code . . . . . . . . . . 164 23 Important notes . . . . . . . . . . . . . . ...
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Description 1 Description The ST7DALIF2 device is a member of the ST7 microcontroller family designed for DALI applications running from 2.4 to 5.5 V. Different package options offer I/O pins. All devices are based on a common ...
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ST7DALIF2 2 Device summary Table 1. Device summary Features Program memory RAM (stack) Data EEPROM Peripherals Operating supply CPU frequency Operating temperature Packages ST7DALIF2 8 Kbytes 384 (128) bytes 256 bytes Lite Timer with Watchdog, Autoreload Timer with 32 MHz ...
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Block diagram 3 Block diagram Figure 1. General block diagram CLKIN OSC1 OSC2 RESET 12/171 PLL 8MHz -> 32MHz Int 1MHz PLL PLL Ext. OSC Internal 1MHz to ...
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ST7DALIF2 4 Pin description Figure 2. 20-pin SO package pinout CLKIN/AIN4/PB4 DALIIN/AIN6/PB6 RESET 3 SS/AIN0/PB0 4 ei0 SCK/AIN1/PB1 ei3 5 MISO/AIN2/PB2 6 MOSI/AIN3/PB3 7 8 ei2 ei1 AIN5/PB5 9 10 (HS) 20mA high sink ...
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Pin description Legend / Abbreviations for Type: In/Output level: Output level: Port and control configuration: ● Input: ● Output: The RESET configuration of each pin is shown in bold which is valid as long as the device is in reset ...
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ST7DALIF2 Table 2. Device pin description (continued) Level Pin Pin name no. 11 PA7/DALIOUT I PA6 /MCO/ 12 I/O C ICCCLK/BREAK PA5 /ATPWM3 ICCDATA 14 PA4/ATPWM2 I PA3/ATPWM1 I ...
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Register and memory map 5 Register and memory map As shown in Figure registers. The available memory locations consist of 128 bytes of register locations, 384 bytes of RAM, 256 bytes of data EEPROM and 8 Kbytes of user program ...
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ST7DALIF2 Table 3. Hardware register map Address Block 0000h 0001h Port A 0002h 0003h 0004h Port B 0005h 0006h 0007h 0008h 0009h LITE 000Ah TIMER 2 000Bh 000Ch 000Dh 000Eh 000Fh 0010h 0011h 0012h 0013h 0014h 0015h AUTO- 0016h RELOAD ...
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Register and memory map Table 3. Hardware register map (continued) Address Block 0034h 0035h ADC 0036h 0037h ITC 0038h MCC Clock 0039h and 003Ah Reset 003Bh 003Ch ITC 003Dh to 003Fh 0040h 0041h 0042h DALI 0043h 0044h 0045h 0046h to ...
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ST7DALIF2 6 Flash program memory 6.1 Introduction The ST7 single voltage extended Flash (XFlash non-volatile memory that can be electrically erased and programmed either on a byte-by-byte basis bytes in parallel. The XFlash devices ...
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Flash program memory Depending on the ICP Driver code downloaded in RAM, FLASH memory programming can be fully customized (number of bytes to program, program locations, or selection of the serial communication interface for downloading). 6.3.2 In application programming (IAP) ...
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ST7DALIF2 mode unexpectedly during a reset. In the application, even if the pin is configured as output, any reset will put it back in input pull-up. Figure 4. Typical ICC interface (See Note 3) APPLICATION POWER SUPPLY 6.5 Memory protection ...
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Flash program memory 6.6 Related documentation For details on Flash programming and ICC protocol, refer to the ST7 Flash Programming Reference Manual and to the ST7 ICC Protocol Reference Manual 6.7 Register description 6.7.1 Flash control/status register (FCSR) This register ...
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ST7DALIF2 7 Data EEPROM 7.1 Introduction The Electrically Erasable Programmable Read Only Memory can be used as a non volatile back-up for storing data. Using the EEPROM requires a basic access protocol described in this chapter. 7.2 Main features ■ ...
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Data EEPROM On this device, Data EEPROM can also be used to execute machine code. Take care not to write to the Data EEPROM while executing from it. This would result in an unexpected code being executed. Write operation (E2LAT=1) ...
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ST7DALIF2 Figure 7. Data EEPROM write operation ROW DEFINITION Byte 1 E2LAT bit E2PGM bit Note programming cycle is interrupted (by a reset action), the integrity of the data in memory is not guaranteed. 7.4 Power saving modes ...
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Data EEPROM If a programming cycle is interrupted (by a RESET action), the memory data will not be guaranteed. 7.6 Data EEPROM readout protection The readout protection is enabled through an option bit (see When this option is selected, the ...
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ST7DALIF2 7.7 Register description 7.8 EEPROM control/status register (EECSR) Read/Write Reset Value: 0000 0000 (00h Bits 7:2 = Reserved, forced by hardware to 0. Bit 1 = E2LAT Latch Access Transfer This bit is set by software. ...
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Central processing unit (CPU) 8 Central processing unit (CPU) 8.1 Introduction This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8- bit data manipulation. 8.2 Main features ● Enable executing 63 basic instructions ● Fast ...
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ST7DALIF2 8.3.1 Accumulator (A) The Accumulator is an 8-bit general purpose register used to hold operands and the results of the arithmetic and logic calculations and to manipulate data. 8.3.2 Index registers (X and Y) These 8-bit registers are used ...
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Central processing unit (CPU) Table 6. Arithmetic management bits (continued) BIt Name Zero (Arithmetic Management bit) This bit is set and cleared by hardware. This bit indicates that the result of the last arithmetic, logical or data manipulation is zero. ...
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ST7DALIF2 8.3.5 Stack pointer register (SP R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W The Stack Pointer is a 16-bit register which is always pointing ...
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Supply, reset and clock management 9 Supply, reset and clock management The device includes a range of utility features for securing the application in critical situations (for example in case of a power brown-out), and reducing the number of external ...
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ST7DALIF2 Table 9. RC control registers RCCR RCCR0 RCCR1 Note: 1 Section 20: Electrical characteristics on page 127 and accuracy of the RC oscillator improve clock stability and frequency accuracy recommended to place a decoupling capacitor, ...
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Supply, reset and clock management Figure 11. PLL output frequency timing diagram When the PLL is started, after reset or wakeup from Halt mode or AWUFH mode, it outputs the clock after a delay of t When the PLL output ...
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ST7DALIF2 9.4.2 RC control register (RCCR) Read / Write Reset Value: 1111 1111 (FFh) 7 CR70 CR60 Bits 7:0 = CR[7:0] RC Oscillator Frequency Adjustment Bits These bits must be written immediately after reset to adjust the RC oscillator frequency ...
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Supply, reset and clock management 9.5 Multi-oscillator (MO) The main clock of the ST7 can be generated by four different source types coming from the multi-oscillator block ( MHz or 32 kHz): ● an external source ● 5 ...
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ST7DALIF2 Table 10. ST7 clock sources Crystal/Ceramic Resonators Internal RC Oscillator or Clock source External Clock External Clock on PB4 Supply, reset and clock management Hardware configuration ST7 OSC1 OSC2 EXTERNAL SOURCE ST7 OSC1 OSC2 C L1 LOAD CAPACITORS ST7 ...
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Supply, reset and clock management 9.6 Reset sequence manager (RSM) 9.6.1 Introduction The reset sequence manager includes three RESET sources as shown in ● External RESET source pulse ● Internal LVD RESET (Low Voltage Detection) ● Internal WATCHDOG RESET Note: ...
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ST7DALIF2 9.6.2 Asynchronous external RESET pin The RESET pin is both an input and an open-drain output with integrated R resistor. This pull-up has no fixed value but varies in accordance with the input voltage. It can be pulled low ...
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Supply, reset and clock management 9.6.5 Internal watchdog RESET The RESET sequence generated by a internal Watchdog counter overflow is shown in Figure 15. Starting from the Watchdog counter underflow, the device RESET pin acts as an output that is ...
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ST7DALIF2 The LVD Reset circuitry generates a reset when V ● V when V IT+(LVD) ● V when V IT-(LVD) The LVD function is illustrated in The voltage threshold can be configured by option byte to be low, medium or ...
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Supply, reset and clock management Figure 17. Reset and supply management block diagram RESET 9.7.2 Auxiliary voltage detector (AVD) The Voltage Detector function (AVD) is based on an analog comparison between a V and V reference ...
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ST7DALIF2 Figure 18. Using the AVD to monitor IT+(AVD) V IT-(AVD) V IT+(LVD) V IT-(LVD) AVDF bit AVD INTERRUPT REQUEST IF AVDIE bit = 1 LVD RESET 9.7.3 Low power modes Table 12. Effect of low ...
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Supply, reset and clock management 9.7.4 Register description System integrity (SI) control/status register (SICSR) Read/Write Reset Value: 0000 0xx0 (0xh Bit 7:5 = Reserved, must be kept cleared. Bit 4 = WDGRF Watchdog reset flag This bit ...
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ST7DALIF2 10 Interrupts The ST7 core may be interrupted by one of two different methods: maskable hardware interrupts as listed in the (TRAP). The Interrupt processing flowchart is shown in The maskable interrupts must be enabled by clearing the I ...
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Interrupts An external interrupt triggered on edge will be latched and the interrupt request automatically cleared upon entering the interrupt service routine. Caution: The type of sensitivity defined in the ei source. In case of a NANDed source (as described ...
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ST7DALIF2 Table 15. Interrupt mapping Source N° Description block RESET Reset TRAP Software Interrupt 0 AWU Auto Wake Up Interrupt 1 ei0 External Interrupt 0 2 ei1 External Interrupt 1 3 ei2 External Interrupt 2 4 ei3 External Interrupt 3 ...
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Interrupts 10.4 Interrupt registers 10.4.1 External interrupt control register (EICR) Read/Write Reset Value: 0000 0000 (00h) 7 IS31 IS30 Bit 7:6 = IS3[1:0] ei3 sensitivity These bits define the interrupt sensitivity for ei3 (Port B0) according to Bit 5:4 = ...
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ST7DALIF2 Table 17. External interrupt I/O pin selection ei31 Reset state Bits 5:4 = ei2[1:0] ei2 pin selection These bits are written by software. They select the Port B I/O pin used for the ei2 external ...
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Power saving modes 11 Power saving modes 11.1 Introduction To give a large measure of flexibility to the application in terms of power consumption, five main power saving modes are implemented in the ST7 (see ■ Slow ■ Wait (and ...
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ST7DALIF2 In this mode, the oscillator frequency is divided by 32. The CPU and peripherals are clocked at this lower frequency. Note: Slow-Wait mode is activated when entering Wait mode while the device is already in Slow mode. Figure 21. ...
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Power saving modes Figure 22. Wait mode flowchart 1. Before servicing an interrupt, the CC register is pushed on the stack. The I bit of the CC register is set during the interrupt routine and cleared when the CC register ...
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ST7DALIF2 Figure 23. Halt mode timing overview Figure 24. Halt mode flowchart 1. WDGHALT is an option bit. See option byte section for more details. 2. Peripheral clocked with an external clock source can still be active. 3. Only some ...
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Power saving modes 11.4.1 Halt mode recommendations ● Make sure that an external event is available to wake up the microcontroller from Halt mode. ● When using an external interrupt to wake up the microcontroller, reinitialize the corresponding I/O as ...
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ST7DALIF2 Note: As soon as Active-halt is enabled, executing a HALT instruction while the Watchdog is active does not generate a RESET. This means that the device cannot spend more than a defined delay in this power saving mode. Figure ...
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Power saving modes 11.6 Auto wakeup from Halt mode Auto Wake Up From Halt (AWUFH) mode is similar to Halt mode with the addition of a specific internal RC oscillator for wake-up (Auto Wake Up from Halt Oscillator). Compared to ...
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ST7DALIF2 clocked except those which get their clock supply from another clock generator (such as an external or auxiliary oscillator like the AWU oscillator). ● The compatibility of Watchdog operation with AWUFH mode is configured by the WDGHALT option bit ...
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Power saving modes Figure 29. AWUFH mode flowchart 1. WDGHALT is an option bit. See option byte section for more details. 2. Peripheral clocked with an external clock source can still be active. 3. Only an AWUFH interrupt and some ...
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ST7DALIF2 Bit 2 = AWUF Auto Wake Up Flag This bit is set by hardware when the AWU module generates an interrupt and cleared by software on reading AWUCSR. Writing to this bit does not change its value ...
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Power saving modes Note: If 00h is written to AWUPR, depending on the product, an interrupt is generated immediately after a HALT instruction, or the AWUPR remains unchanged. Table 23. AWU register map and reset values Address Register 7 (Hex.) ...
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ST7DALIF2 12 I/O ports 12.1 Introduction The I/O ports allow data transfer. An I/O port can contain pins. Each pin can be programmed independently either as a digital input or digital output. In addition, specific pins may ...
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I/O ports When enabling/disabling an external interrupt by setting/resetting the related OR register bit, a spurious interrupt is generated if the pin level is low and its edge sensitivity includes falling/rising edge. This is due to the edge detector input ...
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ST7DALIF2 12.2.3 Alternate functions Many ST7s I/Os have one or more alternate functions. These may include output signals from, or input signals to, on-chip peripherals. The describes which peripheral signals can be input/output to which ports. A signal coming from ...
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I/O ports Table 25. I/O port mode options Configuration mode Floating with/without Interrupt Input Pull-up with/without Interrupt Push-pull Output Open Drain (logic level) True Open Drain 1. The diode to VDD is not implemented in the true open drain pads. ...
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ST7DALIF2 Table 26. I/O configurations PAD PAD PAD 1. When the I/O port is in input configuration and the associated alternate function is enabled as an output, reading the DR register will read the alternate function output status. 2. When ...
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I/O ports 12.3 I/O port implementation The hardware implementation on each I/O port depends on the settings in the DDR and OR registers and specific I/O port features such as ADC input or open drain. Switching these I/O ports from ...
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ST7DALIF2 12.7 Device-specific I/O port configuration The I/O port register configurations are summarized as follows. Table 29. Ports PA7:0, PB6:0 with interrupt capability not selected in EISR register floating input pull-up input open drain output push-pull output Table 30. Ports ...
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I/O ports Table 33. I/O port register map and reset values (continued) Address Register label (Hex.) PBDR 0003h Reset Value PBDDR 0004h Reset Value PBOR 0005h Reset Value 68/171 MSB MSB 0 ...
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ST7DALIF2 13 Watchdog timer (WDG) 13.1 Introduction The Watchdog timer is used to detect the occurrence of a software fault, usually generated by external interference or by unforeseen logical conditions, which causes the application program to abandon its normal sequence. ...
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Watchdog timer (WDG) the watchdog is disabled. The value to be stored in the CR register must be between FFh and C0h (see Table ● The WDGA bit is set (watchdog enabled) ● The T6 bit is set to prevent ...
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ST7DALIF2 13.6 Register description 13.6.1 Control register (CR) Read/Write Reset Value: 0111 1111 (7Fh) 7 WDGA Bit 7 = WDGA Activation bit. This bit is set by software and only cleared by hardware after a reset. When WDGA = 1, ...
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Introduction The 12-bit Autoreload Timer can be used for general-purpose timing functions based on a free-running 12-bit upcounter with an input capture register and four PWM ...
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ST7DALIF2 Figure 33. Block diagram ATIC ATCSR f LTIMER (1 ms timebase @ 8MHz) f CPU 32 MHz DCR0H Preload 12-BIT DUTY CYCLE VALUE (shadow) 4 PWM Channels 14.3 Functional description 14.3.1 PWM mode This mode allows up to four ...
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DCRx value the PWMx signals are set to a low level. To obtain a signal on a PWMx pin, the contents of the corresponding DCRx register must be greater than the ...
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ST7DALIF2 Figure 36. PWM signal from 0% to 100% duty cycle f COUNTER COUNTER DCRx=000h DCRx=FFDh DCRx=FFEh DCRx=000h 14.3.2 Output compare mode To use this function, load a 12-bit value in the DCRxH and DCRxL registers. When the 12-bit upcounter ...
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Figure 37. Block diagram of break function BREAK pin (Active Low) Note: The BREAK pin value is latched by the BA bit. 14.3.4 Input capture The 12-bit ATICR register is used to latch the value ...
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ST7DALIF2 14.4 Low power modes Table 36. Effect of low power modes on AT2 timer Mode Slow Wait Active-halt Halt 14.5 Interrupts Table 37. AT2 timer interrupt control bits Interrupt event Overflow event IC event CMP event 1. The CMP ...
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Bits 4:3 = CK[1:0] Counter Clock Selection. These bits are set and cleared by software and cleared by hardware after a reset. They select the clock frequency of the counter. Table 38. Counter clock frequency ...
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ST7DALIF2 software should read the counter value in two consecutive read operations. The CNTRH register can be incremented between the two reads, and in order to be accurate when the software should take this into account when ...
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Bit 1 = OPx PWMx Output Polarity. This bit is read/write by software and cleared by hardware after a reset. This bit selects the polarity of the PWM signal. 0: The PWM signal is not ...
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ST7DALIF2 14.6.10 PWMx duty cycle register low (DCRxL) Read / Write Reset Value: 0000 0000 (00h) 7 DCR7 DCR6 Bits 15:12 = Reserved. Bits 11:0 = DCR[11:0] PWMx Duty Cycle Value This 12-bit value is written by software. It defines ...
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Transfer control register (TRANCR) Read/Write Reset Value: 0000 0001 (01h Bits 7:1 Reserved. Forced by hardware to 0. Bit 0 = TRAN Transfer enable This bit is read/write by software, cleared ...
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ST7DALIF2 Table 39. Register map and reset values (continued) Address Register label (Hex.) PWM3CSR 16 Reset Value DCR0H 17 Reset Value DCR0L 18 Reset Value DCR1H 19 Reset Value DCR1L 1A Reset Value DCR2H 1B Reset Value DCR2L 1C Reset ...
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Lite timer 2 (LT2) 15 Lite timer 2 (LT2) 15.1 Introduction The Lite Timer can be used for general-purpose timing functions based on two free- running 8-bit upcounters, an 8-bit input capture register. 15.2 Main features ■ Real-time ...
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ST7DALIF2 15.3 Functional description 15.3.1 Timebase counter 1 The 8-bit value of Counter 1 cannot be read or written by software. After an MCU reset, it starts incrementing from frequency of f counter rolls over from F9h ...
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Lite timer 2 (LT2) 15.4 Low power modes Table 40. Effect of low power modes on Lite timer Mode Slow Wait Active-halt Halt 15.5 Interrupts Table 41. Interrupt control bits Interrupt event Timebase 1 Event Timebase 2 Event IC Event ...
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ST7DALIF2 Bit 0 = TB2F Timebase 2 Interrupt Flag. This bit is set by hardware and cleared by software reading the LTCSR register. Writing to this bit has no effect Counter 2 overflow 1: A Counter 2 overflow ...
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Lite timer 2 (LT2) Bit Timebase period selection. This bit is set and cleared by software. 0: Timebase period = t 1: Timebase period = t Bit 4 = TB1IE Timebase Interrupt enable. This bit is set ...
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ST7DALIF2 Table 42. Lite timer register map and reset values (continued) Address Register label (Hex.) LTCSR1 0B Reset Value LTICR 0C Reset Value ICIE ICF TB TB1IE ICR7 ICR6 ICR5 ICR4 0 ...
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DALI communication module 16 DALI communication module 16.1 Introduction The DALI Communication Module (DCM serial communication circuit designed for controllable electronic ballasts. Ballasts are the devices used to provide the required starting voltage and operating current for fluorescent, ...
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ST7DALIF2 16.3 DALI standard protocol The DALI protocol uses the bi-phase Manchester asynchronous serial data format. All the bits of the frame are bi-phase encoded except the two stop bits. ■ The transmission rate is about 1.2 kHz. The bi-phase ...
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DALI communication module 16.4 General description The DCM is able to receive or transmit a serial DALI signal using a 16-bit shift register, an edge detector, several data/control registers and arbitration logic. The DCM receives the DALI standard signal from ...
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ST7DALIF2 If the software asks the DCM to receive a "forward frame", the software must switch the DCM to Receive state by clearing the RTS bit and setting the RTA bit in the DCMCR register during the interrupt routine. If ...
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DALI communication module 16.8 Low power modes Table 43. Effect of low power modes on DCM Mode Wait Halt Active-halt 16.9 Interrupts Table 44. Interrupt control bits Interrupt event EOT 16.10 Bi-phase bit detection The clock used for sampling the ...
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ST7DALIF2 Figure 43. DALI signal sampling DALI Signal 4-bit sample clock counter ...
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DALI communication module Figure 44. Example of DALI signal sampling DALI Signal Edge Trigger 4-bit sample clock counter (/16 divider) DCMCSR[3:0] bits Legend CPU f CPU m = (DCMCLK integer value+ Example 1.2 ...
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ST7DALIF2 Bits 7:0 = DCMFA[7:0] Forward Address. These bits are read by software and set/cleared by hardware. These 8 bits are used to store the "forward frame" address byte. 16.11.3 DCM forward data register (DCMFD) Read only Reset Value: 0000 ...
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DALI communication module 1: Acknowledge Bit 1 = RTS Receive/Transmit state. This bit is set/cleared by software and cleared by hardware after a reset. This bit must be set to ’1’ after a forward frame is received backward ...
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ST7DALIF2 0: The DCM is in Transmit state 1: The DCM is in Receive state Bits 3:0 = DCMCSR[3:0] Clock counter value. (Read only) These bits are set/cleared by hardware and read by software. The value of the 4-bit sample ...
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Serial peripheral interface (SPI) 17 Serial peripheral interface (SPI) 17.1 Introduction The Serial Peripheral Interface (SPI) allows full-duplex, synchronous, serial communication with external devices. An SPI system may consist of a master and one or more slaves or a system ...
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ST7DALIF2 Figure 45. Serial peripheral interface block diagram MOSI MISO SOD bit SCK SS 17.4 Functional description A basic example of interconnections between a single master and a single slave is illustrated in Figure The MOSI pins are connected together ...
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Serial peripheral interface (SPI) Figure 46. Single master/ single slave application MASTER MSBit 8-BIT SHIFT REGISTER SPI CLOCK GENERATOR 17.4.1 Slave select management As an alternative to using the SS pin to control the Slave Select signal, the application can ...
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ST7DALIF2 Figure 48. Hardware/software slave select management 17.4.2 Master mode operation In master mode, the serial clock is output on the SCK pin. The clock frequency, polarity and phase are configured by software (refer to the description of the SPICSR ...
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Serial peripheral interface (SPI) Note: While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR register is read. 17.4.3 Slave mode operation In slave mode, the serial clock is received on the SCK ...
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ST7DALIF2 Figure 49, shows an SPI transfer with the four combinations of the CPHA and CPOL bits. The diagram may be interpreted as a master or slave timing diagram where the SCK pin, the MISO pin, the MOSI pin are ...
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Serial peripheral interface (SPI read access to the SPICSR register while the MODF bit is set write to the SPICR register. Note: To avoid any conflicts in an application with multiple slaves, the SS pin must ...
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ST7DALIF2 Figure 50. Clearing the WCOL bit (write collision flag) software sequence Clearing sequence after SPIF = 1 (end of a data byte transfer) Read SPICSR 1st Step 2nd Step Read SPIDR Clearing sequence before SPIF = 1 (during a ...
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Serial peripheral interface (SPI) Figure 51. Single master / multiple slave configuration SCK Slave Device MOSI MOSI SCK Master Device 5V SS 17.5 Low power modes Table 46. Effect of low power modes on SPI Mode Wait Halt 17.5.1 Using ...
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ST7DALIF2 17.6 Interrupts Table 47. Interrupt control bits Interrupt Event SPI End of Transfer Event Master Mode Fault Event Overrun Error Note: The SPI interrupt events are connected to the same interrupt vector (see Interrupts chapter). They generate an interrupt ...
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Serial peripheral interface (SPI) Bit 4 = MSTR Master Mode. This bit is set and cleared by software also cleared by hardware when, in master mode, SS=0 (see Master mode fault (MODF) on page 0: Slave mode 1: ...
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ST7DALIF2 SPIE=1 in the SPICR register cleared by a software sequence (an access to the SPICSR register followed by a write or a read to the SPIDR register). 0: Data transfer is in progress or the flag has ...
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Serial peripheral interface (SPI) 1: Slave deselected 17.7.3 Data I/O register (SPIDR) Read/Write Reset Value: Undefined The SPIDR register is used to transmit and receive data on the serial bus master device, a write to ...
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ST7DALIF2 18 10-bit A/D converter (ADC) 18.1 Introduction The on-chip Analog to Digital Converter (ADC) peripheral is a 10-bit, successive approximation converter with internal sample and hold circuitry. This peripheral has multiplexed analog input channels (refer to ...
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A/D converter (ADC) Figure 52. ADC block diagram f CPU DIV 2 AIN0 AIN1 ANALOG AINx 18.3.2 Input voltage amplifier The input voltage can be amplified by a factor enabling the AMPSEL bit in the ADCDRL ...
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ST7DALIF2 R is the maximum recommended impedance for an analog input signal. If the impedance AIN is too high, this will result in a loss of accuracy due to leakage and sampling not being completed in the alloted time. 18.3.4 ...
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A/D converter (ADC) Table 50. Effect of low power modes on ADC Mode Wait Halt 18.6 Interrupts None. 18.7 Register description 18.7.1 Control/status register (ADCCSR) Read/Write (Except bit 7 read only) Reset Value: 0000 0000 (00h) 7 EOC SPEED ...
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ST7DALIF2 Table 51. Channel selection bits (continued) 1. The number of channels is device dependent. Refer to 18.7.2 Data register high (ADCDRH) Read Only Reset Value: xxxx xxxx (xxh Bits 7:0 = D[9:2] MSB of Analog Converted ...
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A/D converter (ADC) This bit is set and cleared by software. Bit 2 = AMPSEL Amplifier Selection Bit 0: Amplifier is not selected 1: Amplifier is selected Bits 1:0 = D[1:0] LSB of Analog Converted Value Note: When AMPSEL=1 ...
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ST7DALIF2 19 Instruction set 19.1 CPU addressing modes The CPU features 17 different addressing modes which can be classified in 7 main groups (see Table 54). : Table 54. Addressing mode groups Addressing mode Inherent Immediate Direct Indexed Indirect Relative ...
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Instruction set Table 55. CPU addressing mode overview (continued) Relative Direct Relative Indirect Bit Direct Bit Indirect Bit Direct Relative Bit Indirect Relative 19.1.1 Inherent All Inherent instructions consist of a single byte. The opcode fully specifies all the required ...
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ST7DALIF2 . Table 57. Immediate instructions Instruction LD CP BCP AND, OR, XOR ADC, ADD, SUB, SBC 19.1.3 Direct In Direct instructions, the operands are referenced by their memory address. The direct addressing mode consists of two submodes: Direct (short) ...
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Instruction set Indirect (short) The pointer address is a byte, the pointer size is a byte, thus allowing addressing space, and requires 1 byte after the opcode. Indirect (long) The pointer address is a byte, the pointer ...
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ST7DALIF2 19.1.7 Relative mode (direct, indirect) This addressing mode is used to modify the PC register value, by adding an 8-bit signed offset to it. . Table 59. Relative direct and indirect instructions and functions Available relative direct/indirect instructions JRxx ...
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Instruction set Using a prebyte The instructions are described with one to four opcodes. In order to extend the number of available opcodes for an 8-bit CPU (256 opcodes), three different prebyte opcodes are defined. These prebytes modify the meaning ...
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ST7DALIF2 Table 61. Instruction set overview Mnemo Description ADC Add with Carry ADD Addition AND Logical And BCP Bit compare A, memory BRES Bit reset BSET Bit set BTJF Jump if bit is false (0) BTJT Jump if bit is ...
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Instruction set Table 61. Instruction set overview (continued) Mnemo Description JRUGT Jump JRULE Jump Load MUL Multiply NEG Negate (2's compl) NOP No Operation OR OR operation ...
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ST7DALIF2 20 Electrical characteristics 20.1 Parameter conditions Unless otherwise specified, all voltages are referred to V 20.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage ...
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Electrical characteristics Figure 54. Pin input voltage 20.2 Absolute maximum ratings Stresses above those listed as “absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these ...
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ST7DALIF2 Table 63. Current characteristics Symbol I VDD I VSS I IO (1) & (2) I INJ(PIN) ΣI 2) INJ(PIN must never be exceeded. This is implicitly insured if V INJ(PIN) respected, the injection current must be limited ...
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Electrical characteristics 20.3 Operating conditions T = -40 to +85°C unless otherwise specified. A Table 65. General operating conditions Symbol V Supply voltage DD f CPU clock frequency CPU Figure 55. f CPU f [MHz] CPU 8 FUNCTIONALITY NOT GUARANTEED ...
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ST7DALIF2 20.3.1 Operating conditions with low voltage detector (LVD -40 to 85°C, unless otherwise specified A Table 66. Power on/power down operating conditions Symbol Reset release threshold V IT+ (LVD) (V rise) DD Reset generation threshold V IT- ...
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Electrical characteristics Table 68. Operating voltage and startup time Symbol V Internal RC Oscillator operating voltage DD(RC PLL operating voltage DD(x4PLL PLL operating voltage DD(x8PLL) t PLL Startup time STARTUP The RC oscillator and PLL characteristics ...
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ST7DALIF2 Table 70. RC oscillator and PLL characteristics (tested for T 3.3 V Symbol Parameter Internal RC oscillator ( frequency Accuracy of Internal RC oscillator when ACC RC calibrated with (3)(2) RCCR=RCCR1 RC oscillator current I DD(RC) consumption ...
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Electrical characteristics Figure 56. RC Osc Freq vs V (Calibrated with RCCR1 25°C) 1.00 0.90 0.80 0.70 0.60 0.50 2.4 2.6 2.8 3 3.2 VDD (V) Figure 58. Typical RC oscillator Accuracy vs temperature @ V (Calibrated with ...
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ST7DALIF2 Figure 61. PLLx4 Output vs CLKIN frequency ( /2*PLL4) OSC CLKIN 7.00 6.00 5.00 4.00 3.00 2.00 1.00 1 1.5 2 External Input Clock Frequency (MHz -40 to 85°C, unless otherwise specified A Table 71. ...
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Electrical characteristics 20.4.1 Supply current T = -40 to +85° C unless otherwise specified Table 72. Supply current characteristics Symbol Supply current in RUN mode Supply current in Wait mode I DD Supply current in Slow mode Supply ...
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ST7DALIF2 Figure 65. Typical I in Wait vs 4.5 4.0 8Mhz 3.5 4Mhz 3.0 2.5 1MHz 2.0 1.5 1.0 0.5 0.0 2.0 2.5 3.0 3.5 4.0 Vdd (V) Figure 67. Typical I in AWUFH mode ...
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Electrical characteristics 20.5 Clock and timing characteristics Subject to general operating conditions for V Table 74. General timings Symbol t Instruction cycle time c(INST) Interrupt reaction time t = Δt v(IT) t v(IT) 1. Guaranteed by design. Not tested in ...
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ST7DALIF2 Table 77. Typical ceramic resonators f CrOSC Supplier [MHz Resonator characteristics given by the ceramic resonator manufacturer. For more information on these resonators, please consult www.murata.com 2. () means load capacitor built in resonator ...
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Electrical characteristics Table 79. FLASH program memory Symbol Operating voltage for Flash V DD write/erase Programming time for 1~32 bytes (1) t prog Programming time for 1.5 kBytes t Data retention RET N Write erase cycles RW I Supply current ...
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ST7DALIF2 20.7 EMC characteristics Susceptibility tests are performed on a sample basis during product characterization. 20.7.1 Functional EMS (electromagnetic susceptibility) Based on a simple running application on the product (toggling 2 LEDs through I/O ports), the product is stressed by ...
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Electrical characteristics 20.7.2 Electromagnetic interference (EMI) Based on a simple application running on the product (toggling 2 LEDs through the I/O ports), the product is monitored in terms of emission. This emission test is in line with the norm SAE ...
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ST7DALIF2 20.8 I/O port pin characteristics 20.8.1 General characteristics Subject to general operating conditions for V Table 85. General characteristics Symbol Parameter V Input low level voltage IL V Input high level voltage IH Schmitt trigger voltage V (1) hys ...
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Electrical characteristics Figure 71. Typical I 144/171 vs. V with Ta=1 40°C 80 Ta=9 5°C 70 Ta=2 5°C Ta=-45 ° 2.5 3 3.5 4 4.5 ...
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ST7DALIF2 Table 86. Output driving current Symbol Parameter Output low level voltage for a standard I/O pin when 8 pins are sunk at same time (see Figure 75) ( Output low level voltage for a high sink I/O ...
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Electrical characteristics Figure 72. Typical 0.70 0.60 0.50 0.40 0.30 0.20 0.10 0.00 0.01 1 lio (mA) Figure 74. Typical 0.70 0.60 0.50 0.40 0.30 0.20 0.10 0.00 0. lio ...
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ST7DALIF2 Figure 78. Typical 1.20 1.00 0.80 0.60 0.40 0.20 0. lio (mA) Figure 80. Typical 1.20 1.00 0.80 0.60 0.40 0.20 0.00 -0.01 -1 lio(mA) Figure 82. ...
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Electrical characteristics Figure 84. Typical V 0.70 0.60 0.50 0.40 0.30 0.20 0.10 0.00 2.4 2.7 Figure 85. Typical V 0.70 0.60 0.50 0.40 0.30 0.20 0.10 0.00 2.4 Figure 86. Typical V 1.80 1.70 1.60 1.50 1.40 1.30 1.20 ...
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ST7DALIF2 20.9 Control pin characteristics T = -40°C to 85°C, unless otherwise specified A Table 87. Asynchronous RESET pin characteristics Symbol Parameter V Input low level voltage IL V Input high level voltage IH Schmitt trigger voltage V (1) hys ...
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Electrical characteristics RESET pin protection when LVD is enabled When the LVD is enabled recommended to protect the RESET pin as shown in Figure 87 and follow these guidelines: 1. The reset network protects the device against parasitic ...
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ST7DALIF2 RESET pin protection when LVD is disabled When the LVD is disabled recommended to protect the RESET pin as shown in Figure 88 and follow these guidelines: 1. The reset network protects the device against parasitic resets. ...
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Electrical characteristics Table 88. SPI characteristics (continued) Symbol Parameter ( setup time su(SS) ( hold time h(SS) t SCK high and low w(SCKH) t time w(SCKL) t su(MI) Data input setup time t su(SI) t h(MI) ...
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ST7DALIF2 Figure 90. SPI slave timing diagram with CPHA=1 SS INPUT t CPHA=0 CPOL=0 CPHA=1 CPOL=1 t a(SO) see MISO OUTPUT note 2 MOSI INPUT Figure 91. SPI master timing diagram SS INPUT CPHA = 0 CPOL = 0 CPHA ...
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Electrical characteristics 20.11 10-bit ADC characteristics Subject to general operating condition for V Table 89. ADC characteristics Symbol f ADC clock frequency ADC V Conversion voltage range AIN R External input resistor AIN Internal sample and hold C ADC capacitor ...
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ST7DALIF2 Table 90. ADC Accuracy with V Symbol Parameter Total unadjusted error | Offset error Gain Error G Differential linearity | error |E | Integral linearity error L 1. ...
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Electrical characteristics Figure 94. ADC accuracy characteristics with amplifier enabled Digital Result ADCDR 704 E O 108 62.5mV Note: When the AMPSEL bit in the ADCDRL register is set mandatory that f ...
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ST7DALIF2 Table 91. Amplifier characteristics Symbol V Amplifier operating voltage DD(AMP) V Amplifier input voltage IN Amplifier output offset V OFFSET voltage V Step size for monotonicity STEP Linearity Output Voltage Response Amplified Analog input Gain factor Gain Vmax Output ...
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Package characteristics 21 Package characteristics In order to meet environmental requirements, ST offers these devices in different grades of ® ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ...
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ST7DALIF2 21.1 Package mechanical data Figure 96. 20-Pin plastic small outline package, 300-mil width Table 93. 20-pin plastic small outline package dimensions Dim α ...
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Package characteristics Table 94. Thermal characteristics Symbol R thJA T Jmax P Dmax 1. The maximum chip-junction temperature is based on technology characteristics. 2. The maximum power dissipation is obtained from the formula application can be defined ...
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ST7DALIF2 22 Device configuration Each device is available for production in user programmable versions (FLASH) as well as in factory coded versions (FASTROM). ST7FDALI devices are FLASH versions. ST7PDALI devices are Factory Advanced Service Technique ROM (FASTROM) versions: they are ...
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Device configuration Note: When the internal RC oscillator is selected, the OSCRANGE option bits must be kept at their default value in order to select the 256 clock cycle delay (see OPT3:2 = SEC[1:0] Sector 0 size definition These option ...
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ST7DALIF2 OPT3:2 = LVD[1:0] Low voltage detection selection These option bits enable the LVD block with a selected threshold as shown in Table 97. LVD threshold configuration LVD Off Highest Voltage Threshold (∼4.1V) Medium Voltage Threshold (∼3.5V) Lowest Voltage Threshold ...
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... FFh. The selected options are communicated to STMicroelectronics using the correctly completed OPTION LIST appended Refer to application note AN1635 for information on the counter listing returned by ST after code has been transferred. The STMicroelectronics Sales Organization will be pleased to provide detailed information on contractual points. Table 99. Order codes ...
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... Reference/FASTROM Code *FASTROM code name is assigned by STMicroelectronics. FASTROM code must be sent in .S19 format. .Hex extension cannot be processed. ...
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Important notes 23 Important notes 23.1 Execution of BTJX instruction When testing the address $FF with the "BTJT" or "BTJF" instructions, the CPU may perform an incorrect operation when the relative jump is negative and performs an address page change. ...
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ST7DALIF2 The symptom does not occur when the interrupts are handled normally, i.e. when: ● The interrupt request is cleared (flag reset or interrupt mask) within its own interrupt routine ● The interrupt request is cleared (flag reset or interrupt ...
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... Changed section 13.3.1 on page 102: f Changed section 13.7 on page 112 Changed description of WDG HALT option bit (section 15.1 on page 132) Changed description of FMP_R option bit (section 15.1 on page 132) Changed Table 27, “Dedicated STMicroelectronics Development Tools,” on page135 ST7DALIF2 Changes instead of f CLKIN ...
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ST7DALIF2 Table 100. Document revision history (continued) Date 19-Nov-2004 Revision Reset delay in section 11.1.3 on page 51 changed to 30 µs Altered note 1 for section 13.2.3 on page 101 removing references to RESET Removed sentence relating to an ...
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Revision history Table 100. Document revision history (continued) Date 05-Feb-2009 170/171 Revision Updated Section 7.5: Access error handling on page 25 Added caution in Section 9.6: Reset sequence manager (RSM) on page 38 Renamed OSC OSC2 diagram ...
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... ST7DALIF2 Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...