ST7FDALIF2M6TR STMicroelectronics, ST7FDALIF2M6TR Datasheet - Page 70

• Manufacturer Part Number: ST7FDALIF2M6TR
• Description: IC MCU 8BIT 8K FLASH 20-SOIC
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST7FDALIF2M6TR

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: DALI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 15
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 5.5 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-SOIC (7.5mm Width)
• Processor Series: ST7DALI
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 384 B
• Interface Type: DALI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 15
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST7FLITE-SK/RAIS, ST7DALI-EVAL, ST7MDT10-DVP3, ST7MDT10-EMU3, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 7 Channel / 13 bit, 7 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Watchdog timer (WDG)
Note:
13.4
13.4.1
13.5
70/171
1
2
the watchdog is disabled. The value to be stored in the CR register must be between FFh
and C0h (see
●
●
●
Following a reset, the watchdog is disabled. Once activated it cannot be disabled, except by
a reset.
The T6 bit can be used to generate a software reset (the WDGA bit is set and the T6 bit is
cleared).
If the watchdog is activated, the HALT instruction will generate a Reset.
Table 34.
The timing variation shown in
writing to the CR register.
The number of CPU clock cycles applied during the RESET phase (256 or 4096) must be
taken into account in addition to these timings.
Hardware watchdog option
If Hardware Watchdog is selected by option byte, the watchdog is always active and the
WDGA bit in the CR is not used.
Refer to the Option Byte description in
Using Halt mode with the WDG (WDGHALT option)
If Halt mode with Watchdog is enabled by option byte (No watchdog reset on HALT
instruction), it is recommended before executing the HALT instruction to refresh the WDG
counter, to avoid an unexpected WDG reset immediately after waking up the microcontroller.
The same behavior occurs in Active-halt mode.
Interrupts
None.
.
The WDGA bit is set (watchdog enabled)
The T6 bit is set to prevent generating an immediate reset
The T[5:0] bits contain the number of increments which represents the time delay
before the watchdog produces a reset.
WDG counter code
Watchdog timing (f
Table
C0h
FFh
34):
Table 34
CPU
= 8 MHz.)
Section 22.1 on page
is due to the unknown status of the prescaler when
[ms]
min
127
1
161.
[ms]
max
128
2
ST7DALIF2