EP9312-IB Cirrus Logic Inc, EP9312-IB Datasheet - Page 363

• Manufacturer Part Number: EP9312-IB
• Description: IC ARM920T MCU 200MHZ 352-PBGA
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9312-IB

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 352-BGA
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No
• Other names: 598-1259

DS785UM1
RxMI:
RxBI:
RxSQI:
TxLEI:
ECIE:
TxUHI:
MOI:
TxCOI:
Copyright 2007 Cirrus Logic
RxMI is set when a receive frame was discarded due to
the internal FIFO being full. This may be as a result of a
long latency in acquiring the bus or a lack of receive
descriptors. RxMiss is not set in response to a frame that
was partially stored in the FIFO and then discarded due to
lack of FIFO space. This is marked as an Overrun Error in
the Status Queue.
RxBuffers is set when the last available receive descriptor
has been read into the MAC (RxDesEnq = 0). Free
descriptors may still be available in the MAC to
accommodate receive frames.
The Receive Status Queue bit is set when the last free
status queue location has been written (RXStsEnq = 0).
The Transmit Length Error status is set when any
excessively long frame is transferred into the transmit data
FIFO. When this occurs, the MAC assumes an error has
occurred in the transmit descriptor queue, and therefore
stops further transmit DMA transfers. An excessively long
frame is defined as one equal or longer than the value
programmed in the Max Frame Length register. The frame
itself will be terminated with a bad CRC.
When set to 1, this bit indicates that the MAC has
exhausted the transmit descriptor chain.
This bit is set if the MAC runs out of data during a frame
transmission, and the Underrun Halt bit (BMCtl) is set, at
this time the Transmit Descriptor Processor will have been
halted. If the Underrun Halt bit is clear, the MAC will write
an Underrun Status for the frame and continue to the next
transmit frame.
If received frames are lost due to slow movement of
receive data out of the receive buffers, then a receive miss
is said to have occurred. When this happens, the RxMISS
counter is incremented. When the MSB of the count is set,
the MissCnt bit in the Interrupt Status Register is set. If the
MissCntiE bit is set, an interrupt will be generated.
When a transmit collision occurs, the transmit collision
count is incremented. When the MSB of the count is set
the TxCOI bit in the Interrupt Status Register is set. If the
TxCOIE bit is set, an interrupt will be generated.
1/10/100 Mbps Ethernet LAN Controller
EP93xx User’s Guide
9-61
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