EP9312-IB Cirrus Logic Inc, EP9312-IB Datasheet - Page 225

• Manufacturer Part Number: EP9312-IB
• Description: IC ARM920T MCU 200MHZ 352-PBGA
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9312-IB

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 352-BGA
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No
• Other names: 598-1259

HActiveStrtStop
DS785UM1
31
15
Address: 0x8003_0018
Default: 0x0000_0000
Definition: Horizontal Active period Start/Stop register
Bit Descriptions:
Note: When horizontal clock gating is required, set the STRT and STOP fields in the
30
14
RSVD
RSVD
HActiveStrtStop register to the STRT and STOP values in HClkStrtStop + 5. This is a
programming requirement that is easily overlooked.
29
13
28
12
RSVD:
STOP:
27
11
26
10
Copyright 2007 Cirrus Logic
25
9
The STOP value is the horizontal down counter value at
which the HSYNCn signal becomes inactive (stops). When
the Horizontal counter counts down to the STOP value,
the HSYNCn signal goes inactive. Please refer to video
signalling timing diagrams in
STRT:Start - Read/Write
The STRT value is the horizontal down counter value at
which the HSYNCn signal becomes active (starts). When
the Horizontal counter counts down to the STRT value, the
HSYNCn signal goes active (starts). Please refer to video
signalling timing diagrams in
Reserved - Unknown during read
Stop - Read/Write
The STOP value is the value of the Horizontal down
counter at which the HACTIVE signal becomes inactive
(stops). This indicates the end of the active video portion
for the Horizontal line. Please refer to video signalling
timing diagrams in
is an internal block signal. The active video interval is
controlled by the logical OR of VACTIVE and HACTIVE.
Raster Engine With Analog/LCD Integrated Timing and Interface
24
8
23
7
22
6
Figure 7-9
STOP
STRT
21
5
Figure 7-9
Figure 7-9
20
and
4
Figure
19
3
EP93xx User’s Guide
and
and
7-10. HACTIVE
18
2
Figure
Figure
17
1
7-10.
7-10.
16
7-43
0
7