EP9312-IB Cirrus Logic Inc, EP9312-IB Datasheet - Page 244

IC ARM920T MCU 200MHZ 352-PBGA

EP9312-IB

Manufacturer Part Number
EP9312-IB
Description
IC ARM920T MCU 200MHZ 352-PBGA
Manufacturer
Cirrus Logic Inc
Series
EP9r
Datasheets

Specifications of EP9312-IB

Core Processor
ARM9
Core Size
16/32-Bit
Speed
200MHz
Connectivity
EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
352-BGA
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No
Other names
598-1259

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7
7-62
Raster Engine With Analog/LCD Integrated Timing and Interface
EP93xx User’s Guide
DAT:
Copyright 2007 Cirrus Logic
Smart Panel R/W and RS signals must be implemented
via GPIOs and controlled via software. The difference
between the CNT[3:0] value and the ESTRT[3:0] value is
what guarantees set up time for these GPIO signals to the
Smart Panel before the rising edge of the E enable signal
on the E pin.
Data - Read Only
This parallel interface data is input to the EP93xx
processor from the Smart Panel during a read cycle (see
RD bit in the
bits from the Smart Panel are loaded into this DAT field,
respectively, on the falling edge of the ‘E’ enable control
signal on the E pin.
Writing PIFEN = ‘1’ to the
the signals on these pins for Parallel Interface (Smart
Panel) operation:
V_CSYNC --> D7 (Smart Panel)
HSYNC --> D6
BLANK --> D5
P17 --> D4
P3 --> D3
P[2:0] --> D[2:0]
SPCLK --> E
Smart Panel R/W and RS signals must be implemented
via GPIOs and controlled via software.
ParllIfOut
register for read cycle). The D[7:0]
VideoAttribs
register redefines
DS785UM1

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