EP9312-IB Cirrus Logic Inc, EP9312-IB Datasheet - Page 342

IC ARM920T MCU 200MHZ 352-PBGA

EP9312-IB

Manufacturer Part Number
EP9312-IB
Description
IC ARM920T MCU 200MHZ 352-PBGA
Manufacturer
Cirrus Logic Inc
Series
EP9r
Datasheets

Specifications of EP9312-IB

Core Processor
ARM9
Core Size
16/32-Bit
Speed
200MHz
Connectivity
EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
352-BGA
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No
Other names
598-1259

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9
9-40
1/10/100 Mbps Ethernet LAN Controller
EP93xx User’s Guide
9.3 Registers
10.Wait for TxAct in BMSts to be set and then write the appropriate number of descriptors
remaining in the queue to TXDEnq.
0x8001_0000
0x8001_0004
0x8001_0008
0x8001_0010
0x8001_0014
0x8001_0018
0x8001_0020
0x8001_0024
0x8001_0028
0x8001_002C
0x8001_0030 -
0x8001_0034
0x8001_0038
0x8001_003C
0x8001_0040
0x8001_0044
0x8001_0048
0x8001_004C
0x8001_0050 -
0x8001_0055
0x8001_0050 -
0x8001_0057
0x8001_0060
0x8001_0064
0x8001_0068
0x8001_006C
0x8001_0070
0x8001_0074
0x8001_0078
0x8001_0080
0x8001_0084
0x8001_0088
0x8001_0090
0x8001_0094
0x8001_0096
0x8001_0098
0x8001_009C
0x8001_00A0
0x8001_00A4
0x8001_00A6
Address
Copyright 2007 Cirrus Logic
RXStsQBAdd
RXStsQBLen
RXStsQCurL
RXDQCurLe
RXDCurAdd
RXDQBAdd
RXDQBLen
GlIntROSts
RXMissCnt
RXRuntCnt
TXCollCnt
Table 9-3. Ethernet Register List
GlIntMsk
RXDEnq
HashTbl
GlIntFrc
MIICmd
MIIData
GlIntSts
RXBCA
IntStsC
DiagAd
DiagDa
IntStsP
Name
TestCtl
SelfCtl
MIISts
BMSts
BMCtl
RXCtl
TXCtl
IndAd
IntEn
FCT
FCF
AFP
GT
en
n
MAC Receiver Control Register
MAC Transmitter Control Register
MAC Test Control Register
MAC MII Command Register
MAC MII Data Register
MAC MII Status Register
MAC Self Control Register
MAC Interrupt Enable Register
MAC Interrupt Status Preserve Register
MAC Interrupt Status Clear Register
Reserved
MAC Diagnostic Address Register
MAC Diagnostic Data Register
MAC General Timer Register
MAC Flow Control Timer Register
MAC Flow Control Format Register
MAC Address Filter Pointer Register
MAC Individual Address Register, (shares address
space with HashTbl)
MAC Hash Table Register, (shares address space with
IndAd)
MAC Global Interrupt Status Register
MAC Global Interrupt Mask Register
MAC Global Interrupt Read Only Status Register
MAC Global Interrupt Force Register
MAC Transmit Collision Count Register
MAC Receive Miss Count Register
MAC Receive Runt Count Register
MAC Bus Master Control Register
MAC Bus Master Status Register
MAC Receive Buffer Current Address Register
MAC Receive Descriptor Queue Base Address Register
MAC Receive Descriptor Queue Base Length Register
MAC Receive Descriptor Queue Current Length
Register
MAC Receive Descriptor Current Address Register
MAC Receive Descriptor Enqueue Register
MAC Receive Status Queue Base Address Register
MAC Receive Status Queue Base Length Register
MAC Receive Status Queue Current Length Register
Description
DS785UM1

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