EP9312-IB Cirrus Logic Inc, EP9312-IB Datasheet

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... Boot MMU ROM EIDE SRAM & I/F Flash I/F MEMORY AND STORAGE © Copyright 2005 Cirrus Logic (All Rights Reserved) EP9312 Data Sheet Universal Platform Clocks & Timers TM Interrupts & GPIO Keypad & Touch Bus Screen I/F Bridge Processor Bus ...

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... A three-port USB 2.0 Full-speed Host (OHCI) (12 Mbits per second) and three UARTs are included as well. The EP9312 is a high-performance, low-power, RISC- based, single-chip computer built around an ARM920T microprocessor core with a maximum operating clock rate of 200 MHz (184 MHz for industrial conditions). The ARM core operates from a 1 ...

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... Audio Interface ........................................................................................................... 45 AC’97 ........................................................................................................................ 49 LCD Interface ............................................................................................................ 50 ADC ........................................................................................................................... 51 JTAG .......................................................................................................................... 52 352 Pin BGA Package Outline .......................................................................53 352-Ball PBGA Diagram 352 Pin BGA Pinout (Bottom View) ........................................................................... 54 Acronyms and Abbreviations ........................................................................61 Units of Measurement .....................................................................................61 Ordering Information ......................................................................................62 DS515PP7 .................................................................................. 53 © Copyright 2005 Cirrus Logic (All Rights Reserved) EP9312 Universal Platform SOC Processor 3 ...

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... EP9312 Universal Platform SOC Processor List of Figures Figure 1. Timing Diagram Drawing Key ................................................................................. 14 Figure 2. SDRAM Load Mode Register Cycle Timing Measurement ..................................... 15 Figure 3. SDRAM Burst Read Cycle Timing Measurement ................................................... 16 Figure 4. SDRAM Burst Write Cycle Timing Measurement ................................................... 17 Figure 5. SDRAM Auto Refresh Cycle Timing Measurement ................................................ 18 Figure 6 ...

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... Table P. General Purpose Input/Output Pin Assignment ...................................................... 10 Table Q. Reset and Power Management Pin Assignments ................................................... 10 Table R. Hardware Debug Interface ...................................................................................... 11 Table R. 352 Pin Diagram Dimensions .................................................................................. 54 Table S. Pin Descriptions ..................................................................................................... 59 Table T. Pin Multiplex Usage Information ............................................................................. 60 DS515PP7 © Copyright 2005 Cirrus Logic (All Rights Reserved) EP9312 Universal Platform SOC Processor 5 ...

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... EP9312 through the use of laser probing technology. These IDs can then be used to match secure copyrighted content with the ID of the target device the EP9312 is powering, and then deliver the copyrighted information over a secure connection. In addition, secure transactions can benefit by also matching device IDs to server IDs. MaverickKey IDs provide a level of hardware security required for today’ ...

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... I2S Master Clock AC'97 Bit Clock I2S Serial Clock AC'97 Frame AC'97 Frame I2S Frame Clock Clock Clock AC'97 Serial AC'97 Serial Input I2S Serial Input Input AC'97 Serial AC'97 Serial I2S Serial Output Output Output EP9312 ® , and 2 S ports Mode 7 ...

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... EP9312 Universal Platform SOC Processor LCD-specific features include: • Timing and interface signals for digital LCD and TFT displays • Full programmability for either non-interlaced or dual- scan color and grayscale flat panel displays • Dedicated data path to SDRAM controller for improved system performance • ...

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... Two-wire Interface Clock Purpose I/O General Two-wire Interface Data Purpose I/O A real time clock must be connected to RTCXTALI or the EP9312 device will not boot. Table L. Real-Time Clock with Pin Assignments Pin Name - Description Real-Time Clock Oscillator Input Real-Time Clock Oscillator Output EP9312 ...

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... EP9312 Universal Platform SOC Processor Table M. PLL and Clocking Pin Assignments Pin Mnemonic Pin Name - Description XTALI Main Oscillator Input XTALO Main Oscillator Output VDD_PLL Main Oscillator Power GND_PLL Main Oscillator Ground Timers The Watchdog Timer ensures proper operation by requiring periodic attention to prevent a reset-on-time- out ...

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... Internal Boot ROM The Internal 16 Kbyte ROM allows booting from FLASH memory, SPI or UART. Consult the EP93xx User’s Guide for operational details. © Copyright 2005 Cirrus Logic (All Rights Reserved) EP9312 Universal Platform SOC Processor access. Two of these are ...

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... EP9312 Universal Platform SOC Processor Electrical Specifications Absolute Maximum Ratings (All grounds = 0 V, all voltages with respect Parameter Power Supplies Total Power Dissipation Input Current per Pin, DC (Except supply pins) Output current per pin, DC Digital Input voltage Storage temperature Note: 1. Includes all power generated by AC and/or DC output loading. ...

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... Copyright 2005 Cirrus Logic (All Rights Reserved) Universal Platform SOC Processor Symbol Min Max 0.85 × RVDD 0.15 × RVDD 0.65 × RVDD V VDD + 0.3 ih 0.35 × RVDD V -0 -10 il Min Typ Max - 190 240 - 3.5 - 1.0 2 EP9312 Unit µA µA Unit Table ...

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... EP9312 Universal Platform SOC Processor Timings Timing Diagram Conventions This data sheet contains one or more timing diagrams. The following key explains the components used in these diagrams. Any variations are clearly labelled when they occur. Therefore, no additional meaning should be attached unless specifically stated. ...

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... DQMn AD DA Figure 2. SDRAM Load Mode Register Cycle Timing Measurement DS515PP7 Symbol t clk_high t clk_low t clkrf DQd t DQh t DAs t DAh OP-Code © Copyright 2005 Cirrus Logic (All Rights Reserved) Universal Platform SOC Processor Min Typ Max ( HCLK ( HCLK - clk_low clk_high EP9312 Unit ...

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... EP9312 Universal Platform SOC Processor SDRAM Burst Read Cycle SDCLK t d SDCSn RASn CASn SDWEn t DQd DQMn DQMn clk_low DAs DAh n t DAs Figure 3. SDRAM Burst Read Cycle Timing Measurement © Copyright 2005 Cirrus Logic (All Rights Reserved) t clk_high t clkrf t DQh ...

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... SDRAM Burst Write Cycle SDCLK t d SDCSn RASn CASn SDWEn DQMn DS515PP7 t clk_low Figure 4. SDRAM Burst Write Cycle Timing Measurement © Copyright 2005 Cirrus Logic (All Rights Reserved) EP9312 Universal Platform SOC Processor t clk_high t clkrf ...

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... EP9312 Universal Platform SOC Processor SDRAM Auto Refresh Cycle SDCLK SDCSn RASn CASn SDWEn Note: Chip select shown as bus to illustrate multiple devices being put into auto refresh in one access Figure 5. SDRAM Auto Refresh Cycle Timing Measurement 18 t clk_low © Copyright 2005 Cirrus Logic (All Rights Reserved) ...

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... Symbol Min t 0 ADs t t ADh HCLK t - RDpw t - RDd t - DQMd + DAs HCLK t 0 DAh t ADs t RDd t DQMd © Copyright 2005 Cirrus Logic (All Rights Reserved) Universal Platform SOC Processor Typ Max - - - - × (WST1 + HCLK - ADh t RDd t t DAs EP9312 Unit DAh 19 ...

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... EP9312 Universal Platform SOC Processor Static Memory Single Word Write Cycle Parameter AD setup to WRn assert time AD hold from WRn deassert time WRn deassert to CSn deassert time CSn to WRn assert delay time WRn assert time CSn to DQMn assert delay time WRn deassert to DA transition time ...

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... DAh1 t DAs1 © Copyright 2005 Cirrus Logic (All Rights Reserved) Universal Platform SOC Processor Typ Max - - × (WST1 + HCLK × (WST1 + HCLK × (WST1 + HCLK - - × (4 × WST1 + 5) - HCLK - AD2 AD3 t RDd DAh1 DAh1 t t DAs1 EP9312 Unit ADh t DAh2 DAs2 21 ...

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... EP9312 Universal Platform SOC Processor Static Memory 32-bit Write on 8-bit External Bus Parameter AD setup to WRn assert time WRn/DQMn deassert to AD transition time AD hold from WRn deassert time CSn hold from WRn deassert time CSn to WRn assert delay time WRn assert time ...

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... DAh1 t 0 DAh2 t ADd1 t RDpwl t DQMd t DAs1 © Copyright 2005 Cirrus Logic (All Rights Reserved) Universal Platform SOC Processor Typ Max - - × (WST1 + HCLK × (WST1 + HCLK - - × ((2 × WST1 HCLK - ADd2 t RDh t DQMh t t DAh1 DAs2 EP9312 Unit ADh t DAh2 23 ...

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... EP9312 Universal Platform SOC Processor Static Memory 32-bit Write on 16-bit External Bus Parameter AD setup to WRn assert time WRn/DQMn deassert to AD transition time AD hold from WRn deassert time CSn hold from WRn deassert time CSn to WRn assert delay time WRn assert time ...

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... DAs1 DAs1 © Copyright 2005 Cirrus Logic (All Rights Reserved) Universal Platform SOC Processor Typ Max × (WST1 + 1) t HCLK × (WST2 + 1) t HCLK × (WST1 + 2) t HCLK - - - - - - - t t ADd2 ADd3 t t DAh1 DAh1 t t DAs1 DAs2 EP9312 Unit - ADh t DAh2 25 ...

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... EP9312 Universal Platform SOC Processor Static Memory Burst Write Cycle Parameter AD setup to WRn assert time AD hold from WRn deassert time WRN/DQMn deassert to AD transition time CSn hold from WRn deassert time CSn to WRn assert delay time CSn to DQMn assert delay time ...

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... Figure 14. Static Memory Single Read Wait Cycle Timing Measurement DS515PP7 Symbol Min t - WAITd × WAITpw HCLK × CSnd HCLK t WAITd t WAITpw © Copyright 2005 Cirrus Logic (All Rights Reserved) Universal Platform SOC Processor Typ Max × (WST1- HCLK × 510 t - HCLK × HCLK t CSnd EP9312 Unit ...

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... EP9312 Universal Platform SOC Processor Static Memory Single Write Wait Cycle Parameter WAIT to WRn deassert delay time CSn assert to WAIT time WAIT assert time WAIT to CSn deassert delay time AD CSn WRn RDn DQMn DA WAIT Figure 15. Static Memory Single Write Wait Cycle Timing Measurement ...

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... IDCY is honored when going from a asynchronous device (CSx synchronous device (/SDCSy). AD CSnX CSnY WRn RDn DQMn DA WAIT Figure 16. Static Memory Turnaround Cycle Timing Measurement DS515PP7 Symbol Min t - BTcyc t BTcyc © Copyright 2005 Cirrus Logic (All Rights Reserved) Universal Platform SOC Processor Typ Max × (IDCY+ HCLK EP9312 Unit ns 29 ...

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... EP9312 Universal Platform SOC Processor IDE Interface Register Transfers Parameter Cycle time Address valid to DIORn / DIOWn setup DIORn / DIOWn pulse width 8-bit DIORn / DIOWn recovery time DIOWn data setup DIOWn data hold DIORn data setup DIORn data hold DIORn data high impedance state ...

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... C . IORDY is released prior to negation and may be asserted for no more than t A Figure 17. Register Transfer to/from Device © Copyright 2005 Cirrus Logic (All Rights Reserved) Universal Platform SOC Processor IORDY is released prior to negation A C before asserting IORDY. RD EP9312 31 ...

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... EP9312 Universal Platform SOC Processor PIO Data Transfers Parameter Cycle time Address valid to DIORn / DIOWn setup DIORn / DIOWn 16-bit DIORn / DIOWn recovery time DIOWn data setup DIOWn data hold DIORn data setup DIORn data hold DIORn data high impedance state DIORn / DIOWn to address valid hold ...

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... C . IORDY is released prior to negation and may be asserted for no more than t A Figure 18. PIO Data Transfer to/from Device © Copyright 2005 Cirrus Logic (All Rights Reserved) Universal Platform SOC Processor IORDY is released prior to negation A C before asserting IORDY. RD EP9312 33 ...

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... EP9312 Universal Platform SOC Processor Ultra DMA Data Transfer Figure 19 through Figure 28 define the timings associated with all phases of Ultra DMA bursts. The following table contains the values for the timings for each of the Ultra DMA modes. Timing reference levels = 1.5 V ...

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... The definitions for the DIOWn:STOP, DIORn:HDMARDYn:HSTROBE and IORDY:DDMARDYn:DSTROBE signal lines are not in effect until DMARQ and DMACKn are asserted. DS515PP7 t ACK ENV t ACK ENV t AZ ACK Figure 19. Initiating an Ultra DMA data-in Burst © Copyright 2005 Cirrus Logic (All Rights Reserved) Universal Platform SOC Processor ZAD t ZAD t t DVS DVH EP9312 35 ...

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... EP9312 Universal Platform SOC Processor DSTROBE (device) t DVH DD (15:0) (device) DSTROBE (host (15:0) (host) Note: DD (15:0) and DSTROBE signals are shown at both the host and the device to emphasize that cable settling time as well as cable propagation delay shall not allow the data signals to be considered stable at the host until some time after they are driven by the device ...

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... The definitions for the DIOWn:STOP, DIORn:HDMARDYn:HSTROBE and IORDY:DDMARDYn:DSTROBE signal lines are no longer in effect after DMARQ and DMACKn are negated. DS515PP7 ZAH t AZ Figure 22. Device Terminating an Ultra DMA data-in Burst © Copyright 2005 Cirrus Logic (All Rights Reserved) EP9312 Universal Platform SOC Processor t MLI t ACK t ACK t IORDYZ t t DVS DVH CRC t ...

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... EP9312 Universal Platform SOC Processor DMARQ (device) DMACKn (host) STOP (host) HDMARDYn (host) t RFS DSTROBE (device) DD (15:0) IDEDA[2:0] IDECS0n, IDECS1n Note: The definitions for the DIOWn:STOP, DIORn:HDMARDYn:HSTROBE and IORDY:DDMARDYn:DSTROBE signal lines are no longer in effect after DMARQ and DMACKn are negated Figure 23. Host Terminating an Ultra DMA data-in Burst © ...

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... The definitions for the DIOWn:STOP, DIORn:HDMARDYn:HSTROBE and IORDY:DDMARDYn:DSTROBE signal lines are not in effect until DMARQ and DMACKn are asserted. DS515PP7 ACK ENV t ZIORDY t ACK t ACK Figure 24. Initiating an Ultra DMA data-out Burst © Copyright 2005 Cirrus Logic (All Rights Reserved) Universal Platform SOC Processor DVS EP9312 t DVH 39 ...

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... EP9312 Universal Platform SOC Processor HSTROBE (host) t DVH DD (15:0) (host) HSTROBE (device (15:0) (device) Note: DD (15:0) and HSTROBE signals are shown at both the device and the host to emphasize that cable settling time as well as cable propagation delay shall not allow the data signals to be considered stable at the device until some time after they are driven by the host ...

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... The definitions for the DIOWn:STOP, IORDY:DDMARDYn:DSTROBE and DIORn:HDMARDYn:HSTROBE signal lines are no longer in effect after DMARQ and DMACKn are negated. DS515PP7 Figure 27. Host Terminating an Ultra DMA data-out Burst © Copyright 2005 Cirrus Logic (All Rights Reserved) Universal Platform SOC Processor t MLI t ACK t IORDYZ t ACK t t DVS DVH CRC t ACK EP9312 41 ...

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... EP9312 Universal Platform SOC Processor DMARQ (device) DMACKn (host) STOP (host) DDMARDYn (device) t RFS HSTROBE (host) DD (15:0) (host) IDEDA[2:0] IDECS0n, IDECS1n Note: The definitions for the DIOWn:STOP, IORDY:DDMARDYn:DSTROBE and DIORn:HDMARDYn:HSTROBE signal lines are no longer in effect after DMARQ and DMACKn are negated. ...

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... MDIOd © Copyright 2005 Cirrus Logic (All Rights Reserved) Universal Platform SOC Processor Typ Max 10 Mbit 100 Mbit 10 Mbit 100 Mbit mode mode mode mode 400 200 20 260 26 200 20 260 400 200 20 260 26 200 20 260 400 400 - - - - - - - - - - - - 300 300 EP9312 Unit ...

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... EP9312 Universal Platform SOC Processor TXCLK t TXd TXD[3:0]/ TXEN/ TXERR RXCLK RXD[3:0]/ RXDVAL/ RXERR MDC t MDC_high MDIO t (Sourced MDC_per by STA) MDC MDIO (Sourced by PHY TX_high TX_low t TX_per t RXh t RXs t MDC_low t MDIOd Figure 29. Ethernet MAC Timing Measurement © Copyright 2005 Cirrus Logic (All Rights Reserved) ...

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... Data from slave hold time Note: The tspix_clk is programmable by the user. DS515PP7 Symbol t clk_per t clk_high t clk_low t clkrf t DMd t DMs t DMh t DSs t DSh © Copyright 2005 Cirrus Logic (All Rights Reserved) Universal Platform SOC Processor Min Typ Max - tspix_clk - - (tspix_clk (tspix_clk EP9312 Unit ...

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... EP9312 Universal Platform SOC Processor Texas Instruments’ Synchronous Serial Format t clk_per t clk_high SCLK SFRM SSPTXD/ MSB SSPRXD Microwire clk_per clkrf clk_high SCLK t clk_low SFRM MSB SSPTXD 8-bit control SSPRXD 46 t clkrf t clk_low LSB bits Figure 30. TI Single Transfer Timing Measurement ...

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... SCLK (SPO=1) t DMs SSPTXD MSB (master) t DMd t DSs SSPRXD MSB (slave) SFRM DS515PP7 t clk_per t clk_low t DMh t DSh Figure 32. SPI Format with SPH=1 Timing Measurement © Copyright 2005 Cirrus Logic (All Rights Reserved) Universal Platform SOC Processor t clkrf LSB LSB EP9312 47 ...

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... EP9312 Universal Platform SOC Processor 2 Inter-IC Sound - I S Parameter SCLK cycle time SCLK high time SCLK low time SCLK rise/fall time SCLK to LRCLK assert delay time Hold between SCLK assert then LRCLK deassert or Hold between LRCLK deassert then SCLK assert SDI to SCLK deassert setup time ...

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... ASDO t co ASYNC DS515PP7 Symbol t t clk_high clk_low rfout t rfout Figure 34. AC ‘97 Configuration Timing Measurement © Copyright 2005 Cirrus Logic (All Rights Reserved) Universal Platform SOC Processor Min Typ Max - 81.4 - clk_per clk_low clkrf rfin rfout t rfin rfout EP9312 Unit ...

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... EP9312 Universal Platform SOC Processor LCD Interface Parameter SPCLK rise/fall time SPCLK rising edge to control signal transition time SPCLK rising edge to data transition time Data valid time SPCLK HSYNC/ V_CSYNC/ BLANK/ BRIGHT P [17: clkrf Figure 35. LCD Timing Measurement © Copyright 2005 Cirrus Logic (All Rights Reserved) ...

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... Figure 36. ADC Transfer Function © Copyright 2005 Cirrus Logic (All Rights Reserved) Universal Platform SOC Processor Value Units 50K counts (approximate) 0.01% ±15 0.2% 3750 Samples per second 925 Samples per second 500 2 120 Vref EP9312 mV µs ms µV 51 ...

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... EP9312 Universal Platform SOC Processor JTAG Parameter TCK clock period TCK clock high time TCK clock low time TMS / TDI to clock rising setup time Clock rising to TMS / TDI hold time JTAG port clock to output JTAG port high impedance to valid output JTAG port valid output to high impedance ...

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... Pin BGA Package Outline 352-Ball PBGA Diagram (Top View) - (Bottom View) DS515PP7 - Figure 38. 352 Pin PBGA Pin Diagram © Copyright 2005 Cirrus Logic (All Rights Reserved) EP9312 Universal Platform SOC Processor S 0. Ø S Ø 0.10 C Øb 3 DETAIL B ddd C c DETAIL A' 53 ...

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... EP9312 Universal Platform SOC Processor Symbol 26. 23.80 D3 17.95 E 26. 23.80 E3 17.95 e ddd q Note: 1. Controlling Dimension: Millimeter. 2. Primary Datum C and seating plane are defined by the spherical crowns of the solder balls. 3. Dimension b is measured at the maximum solder ball diameter, parallel to Primary Datum C. 4. There shall be a minimum clearance of 0.25 mm between the edge of the solder ball and the body edge. ...

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Y HSYNC DD[1] DD[12] P[2] AD[15] DA[6] DA[4] W P[12] P[9] DD[0] P[5] P[3] DA[7] DA[5] AD[1 V P[16] P[11] P[8] DD[15] DD[13] P[1] U AD[0] P[15] P[10] P[7] P[6] P[4] P[0] V_CSY DD[1 ...

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... EP9312 Universal Platform SOC Processor Pin List The following Plastic Ball Grid Array (PBGA) ball assignment table is sorted in order of ball. Ball Signal Ball A1 CSN[ DA[28] E10 A3 AD[18] E11 A4 DD[8] E12 A5 DD[4] E13 A6 AD[17] E14 A7 RDN E15 A8 RXCLK E16 A9 MIIRXD[0] E17 A10 ...

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... DA[6] PLL_GND Y7 DA[4] ROW[5] Y8 AD[10] DA[8] Y9 DA[1] BLANK Y10 AD[8] P[13] Y11 IDEDA[0] SPCLK Y12 DTRN V_CSYNC Y13 TDO DD[14] Y14 BOOT[0] GND Y15 EEDAT CVDD Y16 ASDO RVDD Y17 SFRM1 GND Y18 RDLED GND Y19 USBP[1] RVDD Y20 ABITCLK EP9312 57 ...

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... The second table (Table signal multiplexing and configuration options. Table summary of the EP9312 pin signals, which illustrates the pad type and pad pull type (if any). The symbols used in the table are defined as follows. (Note: A blank box means Not Applicable (NA) or, for Pull Type, No Pull (NP) ...

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... IDE Chip Select 1 output IDE 8ma IDE Read strobe output IDE 8ma IDE Write strobe output IDE 8ma IDE DMA acknowledge output IDE I PU IDE ready input Power P Digital power, 1.8V Power P Digital power, 3.3V Ground G Digital ground Ground G Digital ground EP9312 59 ...

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... EP9312 Universal Platform SOC Processor Table T illustrates the pin signal multiplexing and configuration options. Physical Pin Name COL[7:0] ROW[7:0] EGPIO[0] EGPIO[1] EGPIO[2] EGPIO[3] EGPIO[4] EGPIO[5] EGPIO[6] EGPIO[7] EGPIO[8] EGPIO[9] EGPIO[10] EGPIO[11] EGPIO[12] EGPIO[13] EGPIO[14] EGPIO[15] ABITCLK ASYNC ASDO ASDI ARSTn SCLK1 ...

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... Celsius Hertz = cycle per second Kilobits per second Kilobyte KiloHertz = 1000 Hz Megabits per second MegaHertz = 1,000 kHz -6 microAmpere = 10 Ampere microsecond = 1,000 nanoseconds = 10 -3 milliAmpere = 10 Ampere millisecond = 1,000 microseconds = 10 -3 milliWatt = 10 Watts -9 nanosecond = 10 seconds -12 picoFarad = 10 Farads Volt Watt EP9312 -6 seconds -3 seconds 61 ...

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... Ordering Information The order numbers for the device are: EP9312-CB EP9312-CBZ -40 ° +85 ° C EP9312-IB -40 ° +85 ° C EP9312-IBZ EP9312 — CBZ Part Number Product Line: Embedded Processor Note the Cirrus Logic Internet site at http://www.cirrus.com to find contact information for your local sales representative. ...