LPC3180FEL320/01,5 NXP Semiconductors, LPC3180FEL320/01,5 Datasheet - Page 36

• Manufacturer Part Number: LPC3180FEL320/01,5
• Description: IC ARM9 MCU 208MHZ 320-LFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC3000r

Specifications of LPC3180FEL320/01,5

• Package / Case: 320-LFBGA
• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 208MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, UART/USART, USB OTG
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 55
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.3 V
• Data Converters: A/D 3x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC31
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 208 MHz
• Operating Supply Voltage: 1.8 V / 3V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: OM10096
• Minimum Operating Temperature: - 40 C
• Package: 320LFBGA
• Device Core: ARM926EJ-S
• Family Name: LPC3100
• Maximum Speed: 208 MHz
• Number Of Programmable I/os: 55
• Interface Type: I2C/SPI/UART/USB
• On-chip Adc: 3-chx10-bit
• Number Of Timers: 2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1018 - EVAL KIT FOR LP3180568-4063 - KIT DEV LPC3180568-4062 - DEBUGGER J-LINK JTAG568-4061 - DEBUGGER U-LINK2 JTAG FOR NXP
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4529; 935286983551

NXP Semiconductors
Table 9.
C
[1]
[2]
LPC3180_01_1
Preliminary data sheet
Symbol Parameter
-
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
CK
CH
CL
d(CV)
h(C)
d(AV)
h(A)
DS
DH
DQSH
DQSL
DQSS
DSS
DSH
DQSD
su(D)
h(D)
L
= 25 pF; T
All values valid for EMC pads set to high slew rate at 1.8V .
DQS_DELAY, see LP3180/01 user manual, SDRAM Memory Controller Chapter, Section 8 DDR DQS delay calibration for details on
configuring this value.
Operating frequency
Clock cycle time
Clock high level width
Clock low level width
control valid delay time
control hold time
address valid delay time
address hold time
DQ & DM output setup time to DQS out
DQ & DM output hold time to DQS out
Write DQS output high width
Write DQS output low width
Write cmd to 1st DQS out latching transition
DQS in falling edge to CK setup time
DQS in falling edge hold time from CK
DQS_in to DQS_DELAY
data input set-up time
data input hold time
EMC DDR SDRAM memory interface dynamic characteristics
amb
= 40
9.3 DDR SDRAM Controller
°
C.
Rev. 00.08 — 20 November 2008
16/32-bit ARM microcontroller with external memory interface
[2]
Min Typical
104
9.6
0.5
0.5
(CMD_DLY x 0.25) + 1.5
(CMD_DLY x 0.25) - 1.5
0.225
0.5
0.5
.5
DQS_DELAY
0.3
0.5
[1]
(CMD_DLY x 0.25) + 1.5
(CMD_DLY x 0.25) - 1.5
0.275
tCK + (CMD_DLY x 0.25)
.5
LPC3180/01
© NXP B.V. 2008. All rights reserved.
Max Unit
MHz
ns
tCK
tCK
ns
ns
ns
ns
tCK
tCK
tCK
tCK
tCK
tCK
tCK
ns
ns
ns
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