LPC3180FEL320/01,5 NXP Semiconductors, LPC3180FEL320/01,5 Datasheet - Page 24

• Manufacturer Part Number: LPC3180FEL320/01,5
• Description: IC ARM9 MCU 208MHZ 320-LFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC3000r

Specifications of LPC3180FEL320/01,5

• Package / Case: 320-LFBGA
• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 208MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, UART/USART, USB OTG
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 55
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.3 V
• Data Converters: A/D 3x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC31
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 208 MHz
• Operating Supply Voltage: 1.8 V / 3V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: OM10096
• Minimum Operating Temperature: - 40 C
• Package: 320LFBGA
• Device Core: ARM926EJ-S
• Family Name: LPC3100
• Maximum Speed: 208 MHz
• Number Of Programmable I/os: 55
• Interface Type: I2C/SPI/UART/USB
• On-chip Adc: 3-chx10-bit
• Number Of Timers: 2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1018 - EVAL KIT FOR LP3180568-4063 - KIT DEV LPC3180568-4062 - DEBUGGER J-LINK JTAG568-4061 - DEBUGGER U-LINK2 JTAG FOR NXP
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4529; 935286983551

NXP Semiconductors
LPC3180_01_1
Preliminary data sheet
Fig 4. Power-up reset
6.24.1 Crystal oscillator
6.23 Reset
6.24 Clocking and power control
OSCILLATOR
RESET_N
SYSCLK
POWER
Reset is accomplished by an active low signal on the RESET_N input pin. A reset pulse
with a minimum width of 10 main oscillator clocks after the oscillator is stable is required to
guarantee a valid chip reset. At power-up, 10 milliseconds should be allowed for the
oscillator to start up and stabilize after V
with a minimum duration of 10 clock pulses will also be applied if the watchdog timer
generates an internal device reset.
The RESET_N pin is located in the RTC power domain. This means that the RTC power
must be present for an external reset to have any effect. The RTC power domain
nominally runs from 1.2 V, but the RESET_N pin can be driven as high as 1.95 V.
Clocking in the LPC3180/01 is designed to be versatile, so that system and peripheral
requirements may be met, while allowing optimization of power consumption. Clocks to
most functions may be turned off if not needed, some peripherals do this automatically.
The LPC3180/01 includes three operational modes that give control over processing
speed and power consumption. In addition, clock rates to different functional blocks may
be controlled by changing clock sources, reconfiguring PLL values, or altering clock
divider configurations. This allows a trade-off of power versus processing speed based on
application requirements.
The main oscillator is the basis for the clocks most chip functions use by default.
Optionally, many functions can be clocked instead by the output of a PLL (with a fixed
397x rate multiplication) which runs from the RTC oscillator. In this mode, the main
oscillator may be turned off unless the USB interface is enabled. If a SYSCLK frequency
other than 13 MHz is required in the application, or if the USB block is not used, the main
oscillator may be used with a frequency of between 1 MHz and 20 MHz.
•
Output frequency up to 50 kHz when using a 13 MHz peripheral clock.
Stable Voltage
Rev. 00.08 — 20 November 2008
16/32-bit ARM microcontroller with external memory interface
Oscillator startup
time 10 mS
DD
reaches operational voltage. An internal reset
Minimum 10
clock times
001aah908_CW
LPC3180/01
© NXP B.V. 2008. All rights reserved.
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