LPC3180FEL320/01,5 NXP Semiconductors, LPC3180FEL320/01,5 Datasheet

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LPC3180/01 16/32-bit ARM microcontroller; hardware floating-point coprocessor, USB On-The-Go, and SDRAM memory interface Rev. 00.08 — 20 November 2008 1. General description The LPC3180/ ARM9-based microcontroller for embedded applications designed for high performance and low power dissipation. To ...

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... NXP Semiconductors 10-bit ADC with input multiplexing from three pins. Real-Time Clock (RTC) with separate power supply and power domain, clocked by a dedicated 32 kHz oscillator. Includes a 128 byte scratch pad memory. The RTC may remain active when the rest of the chip is not powered. ...

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... NXP Semiconductors 4. Block diagram VFP9 ETB ETM9 D-TCM I-TCM ARM 9EJS D-CACHE I-CACHE I-SIDE D-SIDE MMU CTRL CTRL DATA INSTR master layer 0 1 slave port 0 slave port 1 slave port 2 slave port 3 slave port 5 slave port 6 slave port 7 32 bit, 104 MHz ...

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... NXP Semiconductors 5. Pinning information 5.1 Pinning Fig 2. LPC3180/01 package Table 2. LPC3180/01 Pin allocation table Pin Symbol Pin Symbol Row A 1 U6_IRRX/ 2 U5_RX/PIO_INP[20] PIO_INP[21] 5 JTAG1_TMS 6 JTAG1_RTCK [1] 9 n.c. 10 VSS_IOA 13 RTCX_OUT 14 RTCX_IN [1] 17 n.c. 18 n.c. [1] 21 n.c. 22 VDD_PLLHCLK_12 Row B 1 KEY_COL5 2 U7_HCTS/ PIO_INP[22] ...

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... NXP Semiconductors Table 2. LPC3180/01 Pin allocation table Pin Symbol Pin Symbol 13 VSS_RTCOSC 14 VDD_RTCOSC12 [1] 17 n.c. 18 n.c. 21 PLL397_LOOP 22 VDD_PLL397_12 Row D 1 KEY_ROW4 2 KEY_COL0 5 U6_IRTX 6 VDD_CORE12_02 9 U2_TX 10 GPI_11 13 RESET_N 14 n.c. [1] 17 n.c. 18 VDD_COREFXD12_02 19 [1] 21 n.c. 22 VSS_AD Row E 1 KEY_ROW2 2 KEY_ROW5 21 VDD_AD28 22 ADIN1 Row F ...

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... NXP Semiconductors Table 2. LPC3180/01 Pin allocation table Pin Symbol Pin Symbol 1 GPO_13 2 GPO_16 21 RAM_D[07] 22 VSS_RAM Row P 1 GPO_18 2 GPO_22/U7_HRTS 21 RAM_D[04] 22 VDD_RAM Row R 1 GPIO_01 2 GPIO_05 21 VSS_CORE_06 22 VSS_RAM Row T 1 GPIO_03/ 2 GPIO_04 KEY_ROW7 21 RAM_CLKIN 22 RAM_D[01] Row U [1] 1 n.c. 2 MS_DIO1 21 RAM_RAS_N 22 VDD_RAM Row V ...

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... NXP Semiconductors Table 2. LPC3180/01 Pin allocation table Pin Symbol Pin Symbol Row AC 1 I2C1_SDA 2 VSS [1] 5 n.c. 6 n.c. 9 GPO_01 10 GPO_19 [1] 13 n.c. 14 n.c. 17 FLASH_IO[06] 18 FLASH_RDY 21 FLASH_CE_N 22 RAM_A[04] Row AD [1] 1 n.c. 2 n.c. [1] 5 n.c. 6 USB_OE_TP_N 9 GPO_14 10 GPO_20 [1] 13 n.c. 14 n.c. 17 FLASH_WR_N 18 FLASH_IO[07] ...

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... NXP Semiconductors Table 3. LPC 3180/01 Pin description Symbol Pin GPI_07 J1 GPI_08/KEY_COL6/ K2 SPI2_BUSY GPI_09/KEY_COL7 L2 GPI_10/U4_RX K1 GPI_11 D10 GPIO_00 T3 GPIO_01 R1 GPIO_02/KEY_ROW6 U3 GPIO_03/KEY_ROW7 T1 GPIO_04 T2 GPIO_05 R2 GPO_00/ AB9 TST_CLK1 GPO_01 AC9 GPO_02 L4 GPO_03 L1 GPO_04 Y3 GPO_05 AB10 GPO_06 M4 GPO_07 M3 GPO_08 M1 GPO_09 N4 GPO_10 M2 GPO_11 AB1 GPO_12 P3 GPO_13 ...

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... NXP Semiconductors Table 3. LPC 3180/01 Pin description Symbol Pin GPO_21/U4_TX P4 GPO_22/U7_HRTS P2 GPO_23/U2_HRTS A11 HIGHCORE A3 I2C1_SCL Y4 I2C1_SDA AC1 I2C2_SCL AD8 I2C2_SDA AA9 JTAG1_NTRST D7 JTAG1_RTCK A6 JTAG1_TCK B5 JTAG1_TDI B6 JTAG1_TDO A4 JTAG1_TMS A5 KEY_COL0 to D2, F4, C1, C2, E4, KEY_COL5 B1 KEY_ROW0 to G3, F2, E1, F3, D1, KEY_ROW5 E2 MS_BS Y1 MS_DIO0 to MS_DIO3 W2, U2, Y2, V4 ...

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... NXP Semiconductors Table 3. LPC 3180/01 Pin description Symbol Pin RAM_D[16]/ L23 DDR_DQS0 RAM_D[17]/ L21 DDR_DQS1 RAM_D[18]/ K24 DDR_NCLK RAM_D[31:19]/ E24, E23, F21, F24, PIO_SD[12:00] G24, H23, J21, G23, H22, K23, H24, J24, H21 RAM_DQM[3:0] W24, V21, W23, Y24 O RAM_RAS_N U21 RAM_WR_N ...

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... NXP Semiconductors Table 3. LPC 3180/01 Pin description Symbol Pin U5_TX C4 U6_IRRX/ A1 PIO_INP[21] U6_IRTX D5 U7_HCTS/ B2 PIO_INP[22] U7_RX/ C3 PIO_INP[23] U7_TX B3 USB_ATX_INT_N AA7 USB_DAT_VP/ AA8 U5_RX USB_I2C_SCL AC8 USB_I2C_SDA AD7 USB_OE_TP_N AD6 USB_SE0_VM/ AB7 U5_TX VDD12 B14 VDD_AD28 D24, E21 VDD_CORE12_01 to AA2, D6, K21, L3, ...

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... NXP Semiconductors Table 3. LPC 3180/01 Pin description Symbol Pin VDD_RAM G21, F22, J22, K22, P22, U22, Y21, AC24, AA20 VSS AC2, AC3, AC4 VSS_AD D22 VSS_CORE_01 to C20, D8, D16, VSS_CORE_09 J4, R3, R21, AA5, AA10, AB17 VSS_IOA A10 VSS_IOB AB5 VSS_IOC AC16, AD15, AB8 ...

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... NXP Semiconductors 6. Functional description 6.1 Architectural overview The microcontroller is a general purpose 32-bit microprocessor, which offers high performance and very low power consumption. The ARM architecture is based on RISC principles, and the instruction set and related decode mechanism are much simpler than those of microprogrammed CISCs ...

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... NXP Semiconductors 6.3 AHB matrix The microcontroller has a multi-layer AHB matrix for inter-block communication. AHB is the ARM high-speed bus, which is part of the ARM bus architecture. AHB is a high-bandwidth low-latency bus that supports multi-master arbitration and a bus grant/request mechanism. For systems where there is only one bus master (the CPU), or ...

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... NXP Semiconductors 4.0 GB off-chip SDRAM memory 2.0 GB peripherals on AHB matrix slave port 7 1.0 GB peripherals on AHB matrix slave port 6 768 MB peripherals on AHB matrix slave port 5 on-chip memory 0.0 GB Fig 3. LPC3180/01 memory map 6.6 SDRAM memory controller The SDRAM memory controller provides an interface between the system bus and external (off-chip) memory devices ...

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... NXP Semiconductors devices of 64/128/256/512 Mbit in size, as well as DDR SDRAM devices of 64/128/256/512 Mbit in size. The SDRAM controller uses four data ports to allow simultaneous requests from multiple on-chip AHB bus masters. 6.7 NAND flash controllers The LPC3180/01 includes two NAND flash controllers, one for multi-level NAND flash devices and one for single-level NAND flash devices ...

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... NXP Semiconductors status and masked interrupt status registers allow versatile condition evaluation. In addition to peripheral functions, each of the six general purpose input/output pins and 11 general purpose input pins are connected directly to the interrupt controller. 6.10 General purpose parallel I/O Some device pins that are not dedicated to a specific peripheral function have been designed to be general purpose inputs, outputs, or I/Os ...

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... NXP Semiconductors • Uses 32 kHz RTC clock 6.12 USB interface The LPC3180/01 supports USB in either device, host, or OTG configuration. 6.12.1 USB device controller The USB device controller enables 12 Mbit/s data exchange with a USB host controller. It consists of register interface, serial interface engine, endpoint buffer memory and DMA controller ...

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... NXP Semiconductors 6.12.3 USB OTG Controller USB OTG (On-The-Go supplement to the USB 2.0 specification that augments the capability of existing mobile devices and USB peripherals by adding host functionality for connection to USB peripherals. 6.12.3.1 Features • Fully compliant with On-The-Go supplement to the USB Specification 2.0 Revision 1.0. • ...

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... NXP Semiconductors 6.13.2.1 Features • Each high-speed UART has 64 byte Receive and Transmit FIFOs. • Receiver FIFO trigger points and 48 B. • Transmitter FIFO trigger points and 8 B. • Each high-speed UART has an internal baud rate generator. • The high-speed UARTs are designed to support data rates of (2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400, 460800, 921600) bit/s. • ...

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... NXP Semiconductors • DMA support for data transmit and receive. • 1-bit to 16-bit word length. • Choice of LSB or MSB first data transmission. 64 × 16-bit input or output FIFO. • • Bit rates Mbit/s. • Busy input function. • DMA time out interrupt to allow detection of end of reception when using DMA. ...

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... NXP Semiconductors The high-speed timer includes three match registers that are compared to the Timer/Counter value. A match can generate an interrupt and cause the Timer/Counter to either continue to run, stop reset. The high-speed timer also includes two capture registers that can take a snapshot of the Timer/Counter value when an input signal transitions ...

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... NXP Semiconductors • Flag to indicate that a watchdog reset has occurred. • Programmable watchdog pulse output on RESOUT_N pin. • Can be used as a standard timer if watchdog is not used. • Pause control to stop counting when core is in debug state. 6.21 Real-Time Clock (RTC) and battery RAM The RTC runs at 32768 Hz using a very low power oscillator ...

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... NXP Semiconductors • Output frequency kHz when using a 13 MHz peripheral clock. 6.23 Reset Reset is accomplished by an active low signal on the RESET_N input pin. A reset pulse with a minimum width of 10 main oscillator clocks after the oscillator is stable is required to guarantee a valid chip reset. At power-up, 10 milliseconds should be allowed for the ...

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... NXP Semiconductors 6.24.2 PLLs The LPC3180/01 includes three PLLs: one allows boosting the RTC frequency to 13.008896 MHz for use as the primary system clock; one provides the 48 MHz clock required by the USB block; and one provides the basis for the CPU clock, the AHB bus clock, and the main peripheral clock ...

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... NXP Semiconductors 6.24.4 APB bus Many peripheral functions are accessed by on-chip APB busses that are attached to the higher speed AHB bus. The APB bus performs reads and writes to peripheral registers in three peripheral clocks. 6.24.5 FAB bus Some peripherals are placed on a special bus called FAB that allows faster CPU access to those peripheral functions ...

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... NXP Semiconductors 7. Limiting values Table 4. Limiting values for LPC3180/01 In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V supply voltage (1.2 V) DD(1V2) V supply voltage (1.8 V) DD(1V8) V analog supply voltage (3.3 V) DDA(3V3) V supply voltage DD V analog input voltage IA V input voltage ...

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... NXP Semiconductors 8. Static characteristics 8.1 Static characteristics LPC3180/01 Table 5. Static characteristics for the LPC3180/01 − ° ° +85 C, unless otherwise specified. amb Symbol Parameter Conditions V supply voltage core supply voltage for normal DD(1V2) (1.2 V) operation; full frequency range core supply voltage for reduced power ...

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... NXP Semiconductors Table 5. Static characteristics for the LPC3180/01 − ° ° +85 C, unless otherwise specified. amb Symbol Parameter Conditions −(1.5V I I/O latch-up latch DD current I pull-up current 1.8 V inputs with pull-up 3.3 V inputs with pull-up pull-down 1.8 V inputs with pull-down; pd current ...

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... NXP Semiconductors Table 5. Static characteristics for the LPC3180/01 − ° ° +85 C, unless otherwise specified. amb Symbol Parameter Conditions −(1.5V I I/O latch-up latch DD current I pull-up current 1.8 V inputs with pull-up 3.3 V inputs with pull-up pull-down 1.8 V inputs with pull-down; pd current ...

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... NXP Semiconductors Table 5. Static characteristics for the LPC3180/01 − ° ° +85 C, unless otherwise specified. amb Symbol Parameter Conditions V LOW-level 1.8 V outputs output voltage 3.3 V outputs LOW-level output current OFF-state output current no pull-up/down I LOW-level OLS DD short-circuit output current ...

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... NXP Semiconductors [2] Applies to VDD_CORE12_01 to VDD_CORE12_08 pins. [3] Applies to pins VDD_RTC12, VDD_RTCCORE12, and VDD_RTCOSC12. [4] Applies to pins VDD_COREFXD12_01 to VDD_COREFXD12_02, VDD_OSC12, VDD_PLL397_12, VDD_PLLHCLK_12, VDD_PLLUSB_12, and VDD12. [5] Applies to VDD_RAM, VDD_IOC pins. [6] Applies to VDD_IOA, VDD_IOB, and VDD_IOD pins. [7] Referenced to the applicable V for the pin. DD [8] Including voltage on outputs in 3-state mode. ...

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... NXP Semiconductors 1023 1022 1021 1020 1019 1018 7 code out offset error E O (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error ( (4) Integral non-linearity (E ). L(adj) (5) Center of a step of the actual transfer curve. Fig 5. ADC characteristics LPC3180_01_1 Preliminary data sheet ...

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... NXP Semiconductors 9. Dynamic characteristics 9.1 Clocking and I/O Port pins Table 7. Dynamic characteristics − ° ° +85 C, unless otherwise specified. amb Symbol Parameter Reset f external RESET_N pulse width W(RESET_N) External clock f external clock frequency ext Port pins t rise time r t fall time ...

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... NXP Semiconductors EMC_CLK output signal (O) input signal (I) (1) x can represent the following names: address (A), control (C) or data (Q) Fig 6. SDR SDRAM Signal timing LPC3180_01_1 Preliminary data sheet 16/32-bit ARM microcontroller with external memory interface d(x) h( su(D) h(D) 002aad636_CW Rev. 00.08 — 20 November 2008 LPC3180/01 © ...

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... NXP Semiconductors 9.3 DDR SDRAM Controller Table 9. EMC DDR SDRAM memory interface dynamic characteristics ° pF amb Symbol Parameter - Operating frequency t Clock cycle time CK t Clock high level width CH t Clock low level width CL t control valid delay time d(CV) t control hold time ...

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... NXP Semiconductors EMC_CLK_N EMC_CLK_P EMC control and address (1) x can represent the following names: address (A) or control (C) Fig 7. DDR Control timing parameters EMC_CLK_N EMC_CLK command DQS DQ, DM Fig 8. DDR Write timing parameters EMC_CLK_N EMC_CLK command RD DQS DQS_DELAY DQ DQS_DELAY is an internal signal shown for reference only Fig 9 ...

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... NXP Semiconductors 9.4 USB Controller Table 10. Dynamic characteristics USB digital I/O pins − ° ° 3 +85 C, unless otherwise specified. DD(IO) amb Symbol Parameter t bus turnaround time (I/O) TIO t bus turnaround time (O/I) TOI [1] Parameters are valid over operating temperature range unless otherwise specified. ...

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... NXP Semiconductors 9.5 Secure Digital (SD) card interface Table 11. Dynamic characteristics: SD card pin interface − ° ° +85 C for industrial applications; V amb Symbol Parameter T clock cycle time cy(clk) t data input set-up time su(D) t data input hold time h(D) t data output valid delay time ...

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... NXP Semiconductors 9.6 MLC NAND flash memory controller Table 12. Dynamic characteristics of MLC NAND Flash Memory pins Symbol Parameter (from NAND Flash controller perspective) t CE# to RE# time d(CERE) t RE# cycle time RC t RE# high time REH t RE# high to output hi-Z RHZ t RE# pulse width ...

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... NXP Semiconductors CE RE FLASH_IO[0-7] Fig 13. MLC NAND flash controller read timing Table 13. Dynamic characteristics of SLC NAND Flash Memory pins Symbol Parameter (from NAND Flash perspective) t ALE setup time ALS t ALE hold time ALH t ALE to RE# delay AR t CE# access time CEA t CE# setup time ...

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... NXP Semiconductors Table 13. Dynamic characteristics of SLC NAND Flash Memory pins Symbol Parameter (from NAND Flash perspective) t WE# high to RE# low WHR t WE# pulse width WP t RE# high to R/B# RB [1] xxxxT HCLK [2] Rsu = bitfield R_SETUP[3:0] in register SLC_TAC[3:0] for reads [ bitfield R_HOLD[3:0] in register SLC_TAC[7:4] for reads ...

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... NXP Semiconductors READ ALE t t CLS CLH CLE FLASH_IO[0-7] Command Command Fig 15. NAND flash memory read timing LPC3180_01_1 Preliminary data sheet 16/32-bit ARM microcontroller with external memory interface t t ALS ALH CLR Address t CEA Address Rev. 00.08 — 20 November 2008 LPC3180/01 ...

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... NXP Semiconductors STATUS CLS CLH CLE FLASH_IO[0- Command Fig 16. NAND flash memory status timing LPC3180_01_1 Preliminary data sheet 16/32-bit ARM microcontroller with external memory interface t CLR t WHR t IR Rev. 00.08 — 20 November 2008 LPC3180/01 t CEA t COH t RHOH Status t RHZ t REA Data © ...

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... NXP Semiconductors 9.7 SPI controller Table 14. Dynamic characteristics of SPI pins for LPC3180/01 Symbol Parameter T SPI cycle time SPICYC SPI1 t SPI data set-up time SPIDSU t SPI data hold time SPIDH t SPI enable to output data valid time SPIDV t SPI output data hold time ...

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... NXP Semiconductors SCK (CPOL = 0) SCK (CPOL = 1) SPIn_DATIO SPIn_DATIN Fig 18. SPI master timing (CPHA = 1) LPC3180_01_1 Preliminary data sheet 16/32-bit ARM microcontroller with external memory interface SPICLK SPICLKH SPICLKL t SPIDV DATA VALID DATA VALID t t SPIDSU SPIDH DATA VALID DATA VALID 002aad326_CPHA1_CW Rev. 00.08 — 20 November 2008 ...

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... NXP Semiconductors 10. Package outline LFBGA320: plastic low profile fine-pitch ball grid array package; 320 balls; body 0.9 mm ball A1 index area ball index area DIMENSIONS (mm are the original dimensions) A UNIT max. 0.3 1.0 0.35 13.1 mm 1.3 0.2 0.8 0.25 12.9 OUTLINE VERSION ...

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... NXP Semiconductors 11. Appendix This appendix provides compatibility and comparison information between the LPC3180 and the LPC3180/01. 11.1 Compatibility with LPC3180 1. The reset states on 2 pins of each SPI have changed to better fit typical uses of this type of interface. – On reset, the LPC3180 configures the SPI1_CLK and SPI1_DATIO pins as outputs and drives them low ...

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... NXP Semiconductors 8. The bootloader software BootID has changed from 0x34 to 0x35. This may effect software that checks the BootID version. Version 0x35 of the bootloader code should not change the execution requirements of customer code, with the exception of the check for the value of the BootID itself. ...

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... NXP Semiconductors Table 16. Pin comparison 3180 to 3180/01 (power, ground, and internally connected) 3180 Symbol 3180/01 Symbol VDD12 VDD12 [1] VDD12 n.c. VDD_AD28 VDD_AD28 VDD_CORE12_01 to VDD_CORE12_01 to VDD_CORE12_03, VDD_CORE12_03, VDD_CORE12_05 to VDD_CORE12_05 to VDD_CORE12_08 VDD_CORE12_08 VDD_COREFXD12_01, VDD_COREFXD12_01, VDD_COREFXD12_02 VDD_COREFXD12_02 [4] VDD1828 VDD_IOB [1] VDD1828 n.c. [3] VDD_IO1828_01 to VDD_IOA VDD_IO1828_02 ...

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... NXP Semiconductors Table 16. Pin comparison 3180 to 3180/01 (power, ground, and internally connected) 3180 Symbol 3180/01 Symbol VSS VSS [1] VSS n.c. VSS_AD VSS_AD VSS_CORE_01 to VSS_CORE_01 to VSS_CORE_09 VSS_CORE_09 VSS_IO1828_01 VSS_IOD VSS_IO1828_02 VSS_IOA VSS_IO18_01, VSS_IOC VSS_IO18_02, VSS_IO18_04 [1] VSS_IO18_03 n.c. VSS_IO28_01 to VSS_IOD VSS_IO28_03 VSS_OSC VSS_OSC ...

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... NXP Semiconductors Table 16. Pin comparison 3180 to 3180/01 (power, ground, and internally connected) 3180 Symbol 3180/01 Symbol VSS_SDRAM_01 to VSS_RAM VSS_SDRAM_9 [1] VSS_SDRAM_10 n.c. [2] [1] i.c. n.c [1] n.c. means not connected. [2] These pins are connected internally and must be left unconnected in an application. [3] VDD_IOA is a voltage domain name change only the 1 power supply for the I/O pins in this domain that may operate from either a 1 ...

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... NXP Semiconductors 12. Abbreviations Table 17. Abbreviations Acronym ADC AHB APB CISC DDR DMA DSP FAB FIFO FIQ GPI GPIO GPO IRQ MAC MMU OHCI OTG PLL PWM RC SDR SPI UART LPC3180_01_1 Preliminary data sheet 16/32-bit ARM microcontroller with external memory interface Description ...

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... NXP Semiconductors 13. Revision history Table 18. Revision history Document ID Release date LPC3180_01_1 <tbd> LPC3180_01_1 Preliminary data sheet 16/32-bit ARM microcontroller with external memory interface Data sheet status Change notice Preliminary data sheet - Rev. 00.08 — 20 November 2008 LPC3180/01 Supersedes - © NXP B.V. 2008. All rights reserved. ...

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... For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail ...

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... NXP Semiconductors 16. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2.1 Key features . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 7 6 Functional description . . . . . . . . . . . . . . . . . . 13 6.1 Architectural overview . . . . . . . . . . . . . . . . . . 13 6.2 Vector Floating Point (VFP) coprocessor . . . . 13 6.3 AHB matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.4 On-chip SRAM . . . . . . . . . . . . . . . . . . . . . . . . 14 6 ...