LPC2939FBD208,551 NXP Semiconductors, LPC2939FBD208,551 Datasheet - Page 17

• Manufacturer Part Number: LPC2939FBD208,551
• Description: IC ARM9 MCU FLASH 768KB 208-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC2900r

Specifications of LPC2939FBD208,551

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 125MHz
• Connectivity: CAN, EBI/EMI, I²C, LIN, SPI, UART/USART, USB, USB OTG
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 152
• Program Memory Size: 768KB (768K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 16K x 8
• Ram Size: 56K x 8
• Voltage - Supply (vcc/vdd): 1.71 V ~ 3.6 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-LQFP
• Processor Series: LPC29
• Core: ARM968E-S
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: OM11027
• Package: 208LQFP
• Device Core: ARM968E-S
• Family Name: LPC2900
• Operating Supply Voltage: 1.8|3.3 V
• Data Bus Width: 16|32 Bit
• Number Of Programmable I/os: 160
• Interface Type: CAN/I2C/LIN/QSPI/UART/USB
• On-chip Adc: 24-chx10-bit
• Number Of Timers: 6
• For Use With: 568-4787 - BOARD EVAL LPC2939
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935287113551

NXP Semiconductors
1.
LPC2939_3
Product data sheet
Only for 1.8 V power sources
6.6.1 Reset and power-up behavior
6.6.2 Reset strategy
6.6.3 IEEE 1149.1 interface pins (JTAG boundary-scan test)
6.6 Reset, debug, test, and power description
The LPC2939 contains external reset input and internal power-up reset circuits. This
ensures that a reset is extended internally until the oscillators and flash have reached a
stable state. See
Section 9
the reset pin.
Table 4.
At activation of the RST pin the JTAGSEL pin is sensed as logic LOW. If this is the case
the LPC2939 is assumed to be connected to debug hardware, and internal circuits
re-program the source for the BASE_SYS_CLK to be the crystal oscillator instead of the
Low-Power Ring Oscillator (LP_OSC). This is required because the clock rate when
running at LP_OSC speed is too low for the external debugging environment.
The LPC2939 contains a central module, the Reset Generator Unit (RGU) in the Power,
Clock and Reset Subsystem (PCRSS), which controls all internal reset signals towards
the peripheral modules. The RGU provides individual reset control as well as the
monitoring functions needed for tracing a reset back to source.
The LPC2939 contains boundary-scan test logic according to IEEE 1149.1, also referred
to in this document as Joint Test Action Group (JTAG). The boundary-scan test pins can
be used to connect a debugger probe for the embedded ARM processor. Pin JTAGSEL
selects between boundary-scan mode and debug mode.
scan test pins.
Table 5.
Symbol
RST
Symbol
JTAGSEL
TRST
TMS
TDI
TDO
TCK
for characteristics of the several start-up and initialization times.
Reset pin
IEEE 1149.1 boundary-scan test and debug interface
Direction
IN
Description
TAP controller select input. LOW level selects ARM debug mode and HIGH level
selects boundary scan and flash programming; pulled up internally
test reset input; pulled up internally (active LOW)
test mode select input; pulled up internally
test data input, pulled up internally
test data output
test clock input
All information provided in this document is subject to legal disclaimers.
Section 8
Rev. 03 — 7 April 2010
for trip levels of the internal power-up reset circuit
Description
external reset input, active LOW; pulled up internally
ARM9 microcontroller with CAN, LIN, and USB
Table 5
shows the boundary-
LPC2939
© NXP B.V. 2010. All rights reserved.
Table 4
1
. See
shows
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