ATSAM3S4CA-CU Atmel, ATSAM3S4CA-CU Datasheet - Page 939

• Manufacturer Part Number: ATSAM3S4CA-CU
• Description: IC MCU 32BIT 256KB FLASH 100BGA
• Manufacturer: Atmel
• Series: SAM3Sr

Specifications of ATSAM3S4CA-CU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 79
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 1.95 V
• Data Converters: A/D 16x10/12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LFBGA
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3S-EK
• Package: 100LFBGA
• Device Core: ARM Cortex M3
• Family Name: AT91
• Maximum Speed: 64 MHz
• Operating Supply Voltage: 1.8|3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 79
• Interface Type: I2C/I2S/SPI/UART/USART/USB
• On-chip Adc: 16-chx12-bit
• On-chip Dac: 2-chx12-bit
• Number Of Timers: 6
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

37.6.2.5
6500C–ATARM–8-Feb-11
Endpoints Without Dual-Banks
Endpoints With Dual-Banks
Transmit Data Cancellation
Some endpoints have dual-banks whereas some endpoints have only one bank. The procedure
to cancel transmission data held in these banks is described below.
To see the organization of dual-bank availability refer to
There are two possibilities: In one case, TXPKTRDY field in UDP_CSR has already been set. In
the other instance, TXPKTRDY is not set.
There are two possibilities: In one case, TXPKTRDY field in UDP_CSR has already been set. In
the other instance, TXPKTRDY is not set.
• TXPKTRDY is not set:
• TXPKTRDY has already been set:
• TXPKTRDY is not set:
• TXPKTRDY has already been set:
– Reset the endpoint to clear the FIFO (pointers). (See,
– Clear TXPKTRDY so that no packet is ready to be sent
– Reset the endpoint to clear the FIFO (pointers). (See,
– Reset the endpoint to clear the FIFO (pointers). (See,
– Clear TXPKTRDY and read it back until actually read at 0.
– Set TXPKTRDY and read it back until actually read at 1.
– Clear TXPKTRDY so that no packet is ready to be sent.
– Reset the endpoint to clear the FIFO (pointers). (See,
Endpoint
Endpoint
Endpoint
Endpoint
Register”.)
Register”.)
Register”.)
Register”.)
Table 37-1 ”USB Endpoint
SAM3S Preliminary
Section 37.7.9 ”UDP Reset
Section 37.7.9 ”UDP Reset
Section 37.7.9 ”UDP Reset
Section 37.7.9 ”UDP Reset
Description”.
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