ATSAM3S4CA-CU Atmel, ATSAM3S4CA-CU Datasheet - Page 131

• Manufacturer Part Number: ATSAM3S4CA-CU
• Description: IC MCU 32BIT 256KB FLASH 100BGA
• Manufacturer: Atmel
• Series: SAM3Sr

Specifications of ATSAM3S4CA-CU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 79
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 1.95 V
• Data Converters: A/D 16x10/12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LFBGA
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3S-EK
• Package: 100LFBGA
• Device Core: ARM Cortex M3
• Family Name: AT91
• Maximum Speed: 64 MHz
• Operating Supply Voltage: 1.8|3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 79
• Interface Type: I2C/I2S/SPI/UART/USART/USB
• On-chip Adc: 16-chx12-bit
• On-chip Dac: 2-chx12-bit
• Number Of Timers: 6
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

10.17.1.4
10.17.1.5
6500C–ATARM–8-Feb-11
B
BLE
B.W
BEQ
BEQ.W
BL
BX
BXNE
BLX
Condition flags
Examples
loopA
ng
target ; Branch to target within 16MB range
target ; Conditionally branch to target
target ; Conditionally branch to target within 1MB
funC
LR
R0
R0
; Branch to loopA
; Conditionally branch to label ng
; Branch with link (Call) to function funC, return address
; stored in LR
; Return from function call
; Conditionally branch to address stored in R0
; Branch with link and exchange (Call) to a address stored
; in R0
Bcond is the only conditional instruction that is not required to be inside an IT block. However, it
has a longer branch range when it is inside an IT block.
These instructions do not change the flags.
• do not use PC in the BLX instruction
• for BX and BLX, bit[0] of Rm must be 1 for correct execution but a branch occurs to the target
• when any of these instructions is inside an IT block, it must be the last instruction of the IT
address created by changing bit[0] to 0
block.
SAM3S Preliminary
131