ATSAM3S4CA-CU Atmel, ATSAM3S4CA-CU Datasheet - Page 661

• Manufacturer Part Number: ATSAM3S4CA-CU
• Description: IC MCU 32BIT 256KB FLASH 100BGA
• Manufacturer: Atmel
• Series: SAM3Sr

Specifications of ATSAM3S4CA-CU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 79
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 1.95 V
• Data Converters: A/D 16x10/12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LFBGA
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3S-EK
• Package: 100LFBGA
• Device Core: ARM Cortex M3
• Family Name: AT91
• Maximum Speed: 64 MHz
• Operating Supply Voltage: 1.8|3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 79
• Interface Type: I2C/I2S/SPI/UART/USART/USB
• On-chip Adc: 16-chx12-bit
• On-chip Dac: 2-chx12-bit
• Number Of Timers: 6
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Figure 32-5. Receiver Ready
32.5.2.4
Figure 32-6. Receiver Overrun
32.5.2.5
Figure 32-7. Parity Error
32.5.2.6
6500C–ATARM–8-Feb-11
6500C–ATARM–8-Feb-11
RXRDY
URXD
RXRDY
OVRE
URXD
RXRDY
URXD
PARE
S
S
Receiver Overrun
Parity Error
Receiver Framing Error
D0
D0
S
D1
D1
D0
D2
D2
If UART_RHR has not been read by the software (or the Peripheral Data Controller or DMA
Controller) since the last transfer, the RXRDY bit is still set and a new character is received, the
OVRE status bit in UART_SR is set. OVRE is cleared when the software writes the control regis-
ter UART_CR with the bit RSTSTA (Reset Status) at 1.
Each time a character is received, the receiver calculates the parity of the received data bits, in
accordance with the field PAR in UART_MR. It then compares the result with the received parity
bit. If different, the parity error bit PARE in UART_SR is set at the same time the RXRDY is set.
The parity bit is cleared when the control register UART_CR is written with the bit RSTSTA
(Reset Status) at 1. If a new character is received before the reset status command is written,
the PARE bit remains at 1.
When a start bit is detected, it generates a character reception when all the data bits have been
sampled. The stop bit is also sampled and when it is detected at 0, the FRAME (Framing Error)
bit in UART_SR is set at the same time the RXRDY bit is set. The FRAME bit remains high until
the control register UART_CR is written with the bit RSTSTA at 1.
D1
D3
D3
D2
D4
D4
D3
D5
D5
D4
D6
D6
D5
D7
D7
D6
P
Wrong Parity Bit
P
D7
stop
P
S
S
stop
D0
Read UART_RHR
D0
D1
D1
D2
D2
D3
RSTSTA
D3
SAM3S Preliminary
SAM3S Preliminary
D4
D4
D5
D5
D6
D6
D7
D7
P
P
stop
RSTSTA
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