AT32UC3B1256-Z1UR Atmel, AT32UC3B1256-Z1UR Datasheet - Page 534

MCU AVR32 256K FLASH 48-QFN

AT32UC3B1256-Z1UR

Manufacturer Part Number
AT32UC3B1256-Z1UR
Description
MCU AVR32 256K FLASH 48-QFN
Manufacturer
Atmel
Series
AVR®32 UC3r
Datasheet

Specifications of AT32UC3B1256-Z1UR

Package / Case
48-QFN Exposed Pad
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Operating Temperature
-40°C ~ 85°C
Speed
60MHz
Number Of I /o
28
Core Processor
AVR
Program Memory Type
FLASH
Ram Size
32K x 8
Program Memory Size
256KB (256K x 8)
Data Converters
A/D 6x10b
Oscillator Type
Internal
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Connectivity
I²C, IrDA, SPI, SSC, UART/USART, USB
Core Size
32-Bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
32059J–12/2010
Figure 24-6. Synchronized Period or Duty Cycle Update
To prevent overwriting the CUPDx by software, the user can use status events in order to syn-
chronize his software. Two methods are possible. In both, the user must enable the dedicated
interrupt in IER at PWM Controller level.
The first method (polling method) consists of reading the relevant status bit in ISR Register
according to the enabled channel(s). See
The second method uses an Interrupt Service Routine associated with the PWM channel.
Note:
Figure 24-7. Polling Method
Note:
Reading the ISR register automatically clears CHIDx flags.
Polarity and alignment can be modified only when the channel is disabled.
End of Cycle
Acknoledgement and clear previous register state
The last write has been taken into account
CPRDx
Update of the Period or Duty Cycle
Writing in CPD field
Writing in CUPDx
1
User’s Writing
CUPDx Value
CHIDx = 1
ISR Read
Figure
24-7.
0
CDTYx
CMRx.CPD
AT32UC3B
534

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