AT32UC3B1256-Z1UR Atmel, AT32UC3B1256-Z1UR Datasheet - Page 147

• Manufacturer Part Number: AT32UC3B1256-Z1UR
• Description: MCU AVR32 256K FLASH 48-QFN
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3B1256-Z1UR

• Package / Case: 48-QFN Exposed Pad
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 60MHz
• Number Of I /o: 28
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Program Memory Size: 256KB (256K x 8)
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Connectivity: I²C, IrDA, SPI, SSC, UART/USART, USB
• Core Size: 32-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

15.5.2
Name:
Access Type:
Offset:
Reset Value:
•
•
•
•
32059J–12/2010
ARBT: Arbitration Type
FIXED_DEFMSTR: Fixed Default Master
DEFMSTR_TYPE: Default Master Type
SLOT_CYCLE: Maximum Number of Allowed Cycles for a Burst
31
23
15
–
–
–
7
0: Round-Robin Arbitration
1: Fixed Priority Arbitration
This is the number of the Default Master for this slave. Only used if DEFMSTR_TYPE is 2. Specifying the number of a master
The size of this field depends on the number of masters. This size is log2(number of masters).
0: No Default Master
At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.
This results in a one cycle latency for the first access of a burst transfer or for a single access.
1: Last Default Master
At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having
This results in not having one cycle latency when the last master tries to access the slave again.
2: Fixed Default Master
At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number
This results in not having one cycle latency when the fixed master tries to access the slave again.
When the SLOT_CYCLE limit is reached for a burst, it may be broken by another master trying to access this slave.
This limit has been placed to avoid locking a very slow slave when very long bursts are used.
This limit must not be very small. Unreasonably small values break every burst and the Bus Matrix arbitrates without performing
which is not connected to the selected slave is equivalent to setting DEFMSTR_TYPE to 0.
accessed it.
that has been written in the FIXED_DEFMSTR field.
any data transfer. 16 cycles is a reasonable value for SLOT_CYCLE.
Slave Configuration Registers
30
22
14
SCFG0...SCFG15
Read/Write
0x40 - 0x7C
0x00000010
–
–
–
6
29
21
13
–
–
5
28
20
12
–
–
4
FIXED_DEFMSTR
SLOT_CYCLE
27
19
11
–
–
3
26
18
10
–
–
2
25
17
–
9
–
1
DEFMSTR_TYPE
AT32UC3B
ARBT
24
16
8
–
0
147