AT32UC3B1256-Z1UR Atmel, AT32UC3B1256-Z1UR Datasheet - Page 382

• Manufacturer Part Number: AT32UC3B1256-Z1UR
• Description: MCU AVR32 256K FLASH 48-QFN
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3B1256-Z1UR

• Package / Case: 48-QFN Exposed Pad
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 60MHz
• Number Of I /o: 28
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Program Memory Size: 256KB (256K x 8)
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Connectivity: I²C, IrDA, SPI, SSC, UART/USART, USB
• Core Size: 32-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

22.7.2.4
22.7.2.5
32059J–12/2010
Endpoint reset
Endpoint activation
• All the endpoints are disabled, except the default control endpoint.
• The default control endpoint is reset (see
• The data toggle sequence of the default control endpoint is cleared.
• At the end of the reset process, the End of Reset (EORST) bit in UDINT interrupt is set.
An endpoint can be reset at any time by writing a one to the Endpoint n Reset (EPRSTn) bit in
the UERST register. This is recommended before using an endpoint upon hardware reset or
when a USB bus reset has been received. This resets:
• The internal state machine of this endpoint.
• The receive and transmit bank FIFO counters.
• All the registers of this endpoint (UECFGn, UESTAn, the Endpoint n Control (UECONn)
Note that the interrupt sources located in the UESTAn register are not cleared when a USB bus
reset has been received.
The endpoint configuration remains active and the endpoint is still enabled.
The endpoint reset may be associated with a clear of the data toggle sequence as an answer to
the CLEAR_FEATURE USB request. This can be achieved by writing a one to the Reset Data
Toggle Set bit in the Endpoint n Control Set register (UECONnSET.RSTDTS).(This will set the
Reset Data Toggle (RSTD) bit in UECONn).
In the end, the user has to write a zero to the EPRSTn bit to complete the reset operation and to
start using the FIFO.
The endpoint is maintained inactive and reset (see
it is disabled (EPENn is written to zero). DTSEQ is also reset.
The algorithm represented on
endpoint.
register), except its configuration (ALLOC, EPBK, EPSIZE, EPDIR, EPTYPE) and the Data
Toggle Sequence (DTSEQ) field of the UESTAn register.
Figure 22-14 on page 383
Section 22.7.2.4
Section 22.7.2.4
must be followed in order to activate an
for more details).
for more details) as long as
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