AT32UC3B1256-Z1UR Atmel, AT32UC3B1256-Z1UR Datasheet - Page 244

• Manufacturer Part Number: AT32UC3B1256-Z1UR
• Description: MCU AVR32 256K FLASH 48-QFN
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3B1256-Z1UR

• Package / Case: 48-QFN Exposed Pad
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 60MHz
• Number Of I /o: 28
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Program Memory Size: 256KB (256K x 8)
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Connectivity: I²C, IrDA, SPI, SSC, UART/USART, USB
• Core Size: 32-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

19.13.6.2
Figure 19-28. Clock Synchronization in Write Mode
Notes:
32059J–12/2010
TWI_RHR
TXCOMP
SVREAD
SCLWS
RXRDY
SVACC
TWCK
1. At the end of the read sequence, TXCOMP is set after a STOP or after a REPEATED_START + an address different from
2. SCLWS is automatically set when the clock synchronization mechanism is started and automatically reset when the mecha-
TWD
SADR.
nism is finished.
Clock Synchronization in Write Mode
S
SADR
As soon as a START is detected
The clock is tied low if the shift register and the RHR is full. If a STOP or REPEATED_START
condition was not detected, it is tied low until RHR is read.
Figure 19-28 on page 244
W
A
DATA0
CLOCK is tied low by the TWI as long as RHR is full
A
describes the clock synchronization in Read mode.
DATA1
DATA0 is not read in the RHR
SCL is stretched on the last bit of DATA1
Rd DATA0
A
Rd DATA1
DATA1
DATA2
NA
Rd DATA2
DATA2
AT32UC3B
S
ADR
244