AT32UC3B1256-Z1UR Atmel, AT32UC3B1256-Z1UR Datasheet - Page 154
AT32UC3B1256-Z1UR
Manufacturer Part Number
AT32UC3B1256-Z1UR
Description
MCU AVR32 256K FLASH 48-QFN
Manufacturer
Atmel
Series
AVR®32 UC3r
Datasheet
1.AT32UC3B164-AUR.pdf
(680 pages)
Specifications of AT32UC3B1256-Z1UR
Package / Case
48-QFN Exposed Pad
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Operating Temperature
-40°C ~ 85°C
Speed
60MHz
Number Of I /o
28
Core Processor
AVR
Program Memory Type
FLASH
Ram Size
32K x 8
Program Memory Size
256KB (256K x 8)
Data Converters
A/D 6x10b
Oscillator Type
Internal
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Connectivity
I²C, IrDA, SPI, SSC, UART/USART, USB
Core Size
32-Bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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16.3
16.4
16.4.1
16.4.2
16.4.3
32059J–12/2010
Block Diagram
Product Dependencies
Power Management
Clocks
Interrupts
Figure 16-1. PDCA Block Diagram
In order to use this module, other parts of the system must be configured correctly, as described
below.
If the CPU enters a sleep mode that disables the PDCA clocks, the PDCA will stop functioning
and resume operation after the system wakes up from sleep mode.
The PDCA has two bus clocks connected: One High Speed Bus clock (CLK_PDCA_HSB) and
one Peripheral Bus clock (CLK_PDCA_PB). These clocks are generated by the Power Man-
ager. Both clocks are enabled at reset, and can be disabled by writing to the Power Manager. It
is recommended to disable the PDCA before disabling the clocks, to avoid freezing the PDCA in
an undefined state.
The PDCA interrupt request lines are connected to the interrupt controller. Using the PDCA
interrupts requires the interrupt controller to be programmed first.
High Speed
Bus Matrix
Controller
Interrupt
Memory
HSB
HSB
HSB
IRQ
Peripheral DMA
HSB to PB
Controller
(PDCA)
Bridge
Handshake Interfaces
Peripheral
Peripheral
Peripheral
Peripheral
(n-1)
AT32UC3B
0
1
2
154
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