AT32UC3B1256-Z1UR Atmel, AT32UC3B1256-Z1UR Datasheet - Page 439

• Manufacturer Part Number: AT32UC3B1256-Z1UR
• Description: MCU AVR32 256K FLASH 48-QFN
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3B1256-Z1UR

• Package / Case: 48-QFN Exposed Pad
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 60MHz
• Number Of I /o: 28
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Program Memory Size: 256KB (256K x 8)
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Connectivity: I²C, IrDA, SPI, SSC, UART/USART, USB
• Core Size: 32-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

22.8.2.11
Register Name:
Access Type:
Offset:
Reset Value:
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•
•
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32059J–12/2010
BYCT: Byte Count
CFGOK: Configuration OK Status
CTRLDIR: Control Direction
RWALL: Read/Write Allowed
PACKET
SHORT
31
23
15
7
-
This field is set with the byte count of the FIFO.
For IN endpoints, incremented after each byte written by the software into the endpoint and decremented after each byte sent to
For OUT endpoints, incremented after each byte received from the host and decremented after each byte read by the software
This field may be updated one clock cycle after the RWALL bit changes, so the user should not poll this field as an interrupt bit.
This bit is updated when the ALLOC bit is written to one.
This bit is set if the endpoint n number of banks (EPBK) and size (EPSIZE) are correct compared to the maximal allowed
If this bit is cleared, the user shall rewrite correct values to the EPBK and EPSIZE fields in the UECFGn register.
This bit is set after a SETUP packet to indicate that the following packet is an IN packet.
This bit is cleared after a SETUP packet to indicate that the following packet is an OUT packet.
Writing a zero or a one to this bit has no effect.
This bit is set for IN endpoints when the current bank is not full, i.e., the user can write further data into the FIFO.
This bit is set for OUT endpoints when the current bank is not empty, i.e., the user can read further data from the FIFO.
This bit is never set if STALLRQ is one or in case of error.
This bit is cleared otherwise.
This bit shall not be used for control endpoints.
the host.
from the endpoint.
number of banks and size for this endpoint and to the maximal FIFO size (i.e. the DPRAM size).
CURRBK
Endpoint n Status Register
STALLEDI/
CRCERRI
30
22
14
6
UESTAn, n in [0..6]
Read-Only 0x0100
0x0130 + (n * 0x04)
0x00000100
BYCT
OVERFI
29
21
13
5
NBUSYBK
NAKINI
28
20
12
4
NAKOUTI
BYCT
27
19
11
3
-
-
UNDERFI
RXSTPI/
CFGOK
26
18
10
2
-
CTRLDIR
RXOUTI
25
17
9
1
DTSEQ
AT32UC3B
RWALL
TXINI
24
16
8
0
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