AT32UC3B1256-Z1UR Atmel, AT32UC3B1256-Z1UR Datasheet - Page 307

MCU AVR32 256K FLASH 48-QFN

AT32UC3B1256-Z1UR

Manufacturer Part Number
AT32UC3B1256-Z1UR
Description
MCU AVR32 256K FLASH 48-QFN
Manufacturer
Atmel
Series
AVR®32 UC3r
Datasheet

Specifications of AT32UC3B1256-Z1UR

Package / Case
48-QFN Exposed Pad
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Operating Temperature
-40°C ~ 85°C
Speed
60MHz
Number Of I /o
28
Core Processor
AVR
Program Memory Type
FLASH
Ram Size
32K x 8
Program Memory Size
256KB (256K x 8)
Data Converters
A/D 6x10b
Oscillator Type
Internal
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Connectivity
I²C, IrDA, SPI, SSC, UART/USART, USB
Core Size
32-Bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Figure 21-3. Fractional Baud Rate Generator
21.6.1.4
32059J–12/2010
CLK_USART/DIV
CLK
CLK_USART
Reserved
Baud Rate in Synchronous Mode or SPI Mode
USCLKS
1
2
3
0
(BRGR). If FP is not 0, the fractional part is activated. The resolution is one eighth of the clock
divider. This feature is only available when using USART normal mode. The fractional Baud
Rate is calculated using the following formula:
The modified architecture is presented below:
If the USART is programmed to operate in synchronous mode, the selected clock is simply
divided by the field CD in BRGR.
In synchronous mode, if the external clock is selected (USCLKS = 3), the clock is provided
directly by the signal on the USART CLK pin. No division is active. The value written in BRGR
has no effect. The external clock frequency must be at least 4.5 times lower than the system
clock.
When either the external clock CLK or the internal clock divided (CLK_USART/DIV) is selected,
the value programmed in CD must be even if the user has to ensure a 50:50 mark/space ratio on
the CLK pin. If the internal clock CLK_USART is selected, the Baud Rate Generator ensures a
50:50 duty cycle on the CLK pin, even if the value programmed in CD is odd.
Baudrate
BaudRate
16-bit Counter
CD
=
---------------------------------------------------------------- -
8 2 Over
Modulus
=
Control
(
FP
SelectedClock
------------------------------------- -
SelectedClock
CD
) CD
+
glitch-free
USCLKS = 3
FP
------ -
logic
FP
8
SYNC
0
>1
CD
1
0
0
1
OVER
Sampling
Divider
FIDI
AT32UC3B
0
1
SYNC
CLK
BaudRate
Sampling
Clock
Clock
307

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