AT32UC3B1256-Z1UR Atmel, AT32UC3B1256-Z1UR Datasheet - Page 320

• Manufacturer Part Number: AT32UC3B1256-Z1UR
• Description: MCU AVR32 256K FLASH 48-QFN
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3B1256-Z1UR

• Package / Case: 48-QFN Exposed Pad
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 60MHz
• Number Of I /o: 28
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Program Memory Size: 256KB (256K x 8)
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Connectivity: I²C, IrDA, SPI, SSC, UART/USART, USB
• Core Size: 32-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

21.6.3.9
21.6.3.10
32059J–12/2010
Multidrop Mode
Transmitter Timeguard
Figure 21-21. Parity Error
If the PAR field in the Mode Register (MR) is programmed to the value 0x6 or 0x07, the USART
runs in Multidrop Mode. This mode differentiates the data characters and the address charac-
ters. Data is transmitted with the parity bit at 0 and addresses are transmitted with the parity bit
at 1.
If the USART is configured in multidrop mode, the receiver sets the PARE parity error bit when
the parity bit is high and the transmitter is able to send a character with the parity bit high when
the Control Register is written with the SENDA bit at 1.
To handle parity error, the PARE bit is cleared when the Control Register is written with the bit
RSTSTA at 1.
The transmitter sends an address byte (parity bit set) when SENDA is written to CR. In this case,
the next byte written to THR is transmitted as an address. Any character written in THR without
having written the command SENDA is transmitted normally with the parity at 0.
The timeguard feature enables the USART interface with slow remote devices.
The timeguard function enables the transmitter to insert an idle state on the TXD line between
two characters. This idle state actually acts as a long stop bit.
The duration of the idle state is programmed in the TG field of the Transmitter Timeguard Regis-
ter (TTGR). When this field is programmed at zero no timeguard is generated. Otherwise, the
transmitter holds a high level on TXD after each transmitted byte during the number of bit peri-
ods programmed in TG in addition to the number of stop bits.
As illustrated in
the programming of a timeguard. TXRDY rises only when the start bit of the next character is
sent, and thus remains at 0 during the timeguard transmission if a character has been written in
THR. TXEMPTY remains low until the timeguard transmission is completed as the timeguard is
part of the current character being transmitted.
Baud Rate
RXRDY
Figure
PARE
Clock
Write
RXD
CR
21-22, the behavior of TXRDY and TXEMPTY status bits is modified by
Start
Bit
D0
D1
D2
D3
D4
D5
D6
D7
Parity
Bad
Bit
Stop
Bit
RSTSTA = 1
AT32UC3B
320