ATTINY84-15MZ Atmel, ATTINY84-15MZ Datasheet - Page 31

• Manufacturer Part Number: ATTINY84-15MZ
• Description: MCU AVR 8K FLASH 15MHZ 20-QFN
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY84-15MZ

• Package / Case: 20-QFN Exposed Pad
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Speed: 16MHz
• Number Of I /o: 12
• Eeprom Size: 512 x 8
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Program Memory Size: 8KB (8K x 8)
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Connectivity: USI
• Core Size: 8-Bit
• Processor Series: ATTINY8x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SPI, UART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 12
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7.8
7.9
7.9.1
7701D–AVR–09/10
128kHz Internal Oscillator
System Clock Prescaler
Switching Time
The 128kHz internal oscillator is a low power oscillator providing a 128kHz clock. The fre-
quency is nominal at 3V and 25°C. This clock may be selected as the system clock by
programming the CKSEL fuses to "0100".
When this clock source is selected, start-up times are determined by the SUT Fuses as shown
in
Table 7-9.
The Atmel
ter – CLKPR. This feature can be used to decrease power consumption when the requirement
for processing power is low. This can be used with all clock source options, and it will affect
the clock frequency of the CPU and all synchronous peripherals. clk
clk
When switching between prescaler settings, the system clock prescaler ensures that no
glitches occur in the clock system and that no intermediate frequency is higher than either the
clock frequency corresponding to the previous setting or the clock frequency corresponding to
the new setting.
The ripple counter that implements the prescaler runs at the frequency of the undivided clock,
which may be faster than the CPU's clock frequency. Hence, it is not possible to determine the
state of the prescaler, even if it were readable, and the exact time it takes to switch from one
clock division to another cannot be exactly predicted.
From the time the CLKPS values are written, it takes between T1 + T2 and T1 + 2*T2 before
the new clock frequency is active. In this interval, twp active clock edges are produced. Here,
T1 is the previous clock period, and T2 is the period corresponding to the new prescaler
setting.
SUT1..0
Table 7-9 on page
FLASH
00
01
10
11
are divided by a factor as shown in
®
ATtiny24/44/84 system clock can be divided by setting the Clock Prescaler Regis-
Power-down and Power-save
Start-up Times for the 128kHz Internal Oscillator
Start-up Time from
31.
6CK
6CK
6CK
Atmel ATtiny24/44/84 [Preliminary]
Table 7-10 on page
Additional Delay from
Reserved
14CK + 64ms
14CK + 4ms
Reset
14CK
33.
I/O
BOD enabled
Fast rising power
Slowly rising power
, clk
Recommended Usage
ADC
, clk
CPU
, and
31