ATTINY84-15MZ Atmel, ATTINY84-15MZ Datasheet - Page 108

• Manufacturer Part Number: ATTINY84-15MZ
• Description: MCU AVR 8K FLASH 15MHZ 20-QFN
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY84-15MZ

• Package / Case: 20-QFN Exposed Pad
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Speed: 16MHz
• Number Of I /o: 12
• Eeprom Size: 512 x 8
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Program Memory Size: 8KB (8K x 8)
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Connectivity: USI
• Core Size: 8-Bit
• Processor Series: ATTINY8x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SPI, UART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 12
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

108
Atmel ATtiny24/44/84 [Preliminary]
In inverting compare output mode, the operation is inverted. The dual-slope operation gives a
lower maximum operation frequency compared to the single-slope operation. However, due to
the symmetric feature of the dual-slope PWM modes, these modes are preferred for motor
control applications.
The main difference between the phase correct, and the phase and frequency correct PWM
mode is the time the OCR1x register is updated by the OCR1x buffer register (see
on page 106
The PWM resolution for the phase and frequency correct PWM mode can be defined by either
ICR1 or OCR1A. The minimum resolution allowed is 2 bits (ICR1 or OCR1A set to 0x0003),
and the maximum resolution is 16 bits (ICR1 or OCR1A set to max). The PWM resolution in
bits can be calculated using the following equation:
In phase and frequency correct PWM mode, the counter is incremented until the counter value
matches either the value in ICR1 (WGM13:0 = 8), or the value in OCR1A (WGM13:0 = 9). The
counter has then reached the top, and changes the count direction. The TCNT1 value will be
equal to top for one timer clock cycle. The timing diagram for the phase and frequency correct
PWM mode is shown on
rect PWM mode when OCR1A or ICR1 is used to define top. The TCNT1 value in the timing
diagram is shown as a histogram for illustrating the dual-slope operation. The diagram
includes non-inverted and inverted PWM outputs. The small horizontal lines on the TCNT1
slopes represent compare matches between OCR1x and TCNT1. The OC1x interrupt flag will
be set when a compare match occurs.
Figure 14-9. Phase and Frequency Correct PWM Mode, Timing Diagram
The timer/counter overflow flag (TOV1) is set on the same timer clock cycle on which the
OCR1x registers are updated with the double buffer value (at bottom). When either OCR1A or
ICR1 is used for defining the top value, the OC1A or ICF1 flag is set accordingly when TCNT1
has reached top. The interrupt flags can then be used to generate an interrupt each time the
counter reaches the top or bottom value.
R
PFCPWM
TCNTn
OCnx
OCnx
Period
=
and
log
---------------------------------- -
log
Figure 14-9 on page
TOP
2
1
+
1
Figure 14-9 on page
2
108).
108. The figure shows phase and frequency cor-
3
4
OCnA Interrupt Flag Set
or ICFn Interrupt Flag Set
(Interrupt on TOP)
(COMnx1:0 = 2)
(COMnx1:0 = 3)
OCRnx/TOP Updateand
TOVn Interrupt Flag Set
(Interrupt on Bottom)
7701D–AVR–09/10
Figure 14-8