ATTINY84-15MZ Atmel, ATTINY84-15MZ Datasheet - Page 120

• Manufacturer Part Number: ATTINY84-15MZ
• Description: MCU AVR 8K FLASH 15MHZ 20-QFN
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY84-15MZ

• Package / Case: 20-QFN Exposed Pad
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Speed: 16MHz
• Number Of I /o: 12
• Eeprom Size: 512 x 8
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Program Memory Size: 8KB (8K x 8)
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Connectivity: USI
• Core Size: 8-Bit
• Processor Series: ATTINY8x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SPI, UART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 12
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

15.3
15.3.1
120
Register Description
Atmel ATtiny24/44/84 [Preliminary]
GTCCR – General Timer/Counter Control Register
Each half period of the external clock applied must be longer than one system clock cycle to
ensure correct sampling. The external clock must be guaranteed to have less than half the
system clock frequency (f
uses sampling, the maximum frequency of an external clock it can detect is half the sampling
frequency (Nyquist sampling theorem). However, due to variation of the system clock fre-
quency and duty cycle caused by oscillator source (crystal, resonator, and capacitor)
tolerances, it is recommended that the maximum frequency of an external clock source is less
than f
An external clock source can not be prescaled.
Figure 15-2. Prescaler for Timer/Counter0
Note:
• Bit 7 – TSM: Timer/Counter Synchronization Mode
Writing the TSM bit to logical one activates the timer/counter synchronization mode. In this
mode, the value that is written to the PSR10 bit is kept, hence keeping the prescaler reset sig-
nal asserted. This ensures that the timer/counter is halted and can be configured without the
risk of advancing during configuration. When the TSM bit is written to logical zero, the PSR10
bit is cleared by hardware, and the timer/counter starts counting.
• Bit 0 – PSR10: Prescaler 0 Reset Timer/Counter n
When this bit is set to one, the timer/counter n prescaler will be reset. This bit is normally
cleared immediately by hardware, except if the TSM bit is set.
Bit
0x23 (0x43)
Read/Write
Initial Value
clk_I/O
1. The synchronization logic on the input pins (
/2.5.
PSR10
clk
T0
I/O
TSM
R/W
7
0
Synchronization
ExtClk
R
6
–
0
< f
Clear
clk_I/O
R
5
–
0
/2) given a 50/50 duty cycle. Because the edge detector
R
4
–
0
T0)
R
3
–
0
is shown in
R
2
–
0
clk
Figure 15-1 on page
T0
R
1
–
0
PSR10
R/W
0
0
7701D–AVR–09/10
119.
GTCCR